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| to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation (http://www.renesas.com) send any inquiries to http://www.renesas.com/inquiry.
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas el ectronics products li sted herein, please confirm the latest product information with a renesas electronics sales office. also , please pay regular and careful attention to additional and different information to be disclosed by rene sas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringeme nt of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electroni cs products or techni cal information descri bed in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyri ghts or other intell ectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any re nesas electronics product, wh ether in whole or in part . 4. descriptions of circuits, software and other related informat ion in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully re sponsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this doc ument, you should comply with the applicable export control laws and regulations and follow the proc edures required by such laws and re gulations. you should not use renesas electronics products or the technology described in this docum ent for any purpose relating to mil itary applicati ons or use by the military, including but not l imited to the development of weapons of mass de struction. renesas electronics products and technology may not be used for or incor porated into any products or systems whose manufacture, us e, or sale is prohibited under any applicable dom estic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing th e information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. renesas electronics products ar e classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product de pends on the product?s quality grade, as indicated below. you must check the qua lity grade of each renesas electronics pr oduct before using it in a particular application. you may not use any renesas electronics produc t for any application categorized as ?speci fic? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. re nesas electronics shall not be in any way liable for any damages or losses incurred by you or third partie s arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intende d where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electr onics data sheets or data books, etc. ?standard?: computers; office equipmen t; communications e quipment; test and measurement equipment; audio and visual equipment; home electronic a ppliances; machine tools; personal electronic equipmen t; and industrial robots. ?high quality?: transportation equi pment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specif ically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support device s or systems), surgical im plantations, or healthcare intervention (e.g. excision, etc.), and any other applicati ons or purposes that pose a di rect threat to human life. 8. you should use the renesas electronics pr oducts described in this document within the range specified by renesas electronics , especially with respect to the maximum ra ting, operating supply voltage range, movement power volta ge range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its produc ts, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate a nd malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physic al injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safe ty design for hardware and software in cluding but not limited to redundancy, fire control and malfunction prevention, appropri ate treatment for aging degradation or an y other appropriate measures. because the evaluation of microcomputer software alone is very difficult , please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesa s electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regul ate the inclusion or use of c ontrolled substances, including wi thout limitation, the eu rohs directive. renesas electronics assumes no liability for damage s or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in w hole or in part, without prio r written consent of renes as electronics. 12. please contact a renesa s electronics sales office if you have any questi ons regarding the informat ion contained in this document or renesas electroni cs products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics. user?s manual pd780816 subseries 8-bit single-chip microcontroller pd780814 pd780816 pd78f0818 document no. u15251ee4v0ud00 date published september 2005 ? nec electronics corporation 2005 printed in germany 2 user?s manual u15251ee4v0ud00 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6 3 user?s manual u15251ee4v0ud00 the information in this document is current as of september, 2005. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? 4 user?s manual u15251ee4v0ud00 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: device availability ordering information product release schedule availability of related technical literature development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics america inc. santa clara, california t el: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (europe) gmbh duesseldorf, germany t el: 0211-65 03 1101 fax: 0211-65 03 1327 sucursal en espa?a madrid, spain tel: 091- 504 27 87 fax: 091- 504 28 60 succursale fran?aise vlizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. singapore tel: 65-6253-8311 fax: 65-6250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 filiale italiana milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 fax: 040-244 45 80 branch sweden taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 united kingdom branch milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 5 user?s manual u15251ee4v0ud00 preface readers this manual has been prepared for engineers who want to understand the functions of the pd780816 subseries and design and develop its application systems and programs. pd780816 subseries: pd780814(a), pd780816(a), pd78f0818(a) pd780814(a1), pd780816(a1) pd780814(a2), pd780816(a2) purpose this manual is intended for users to understand the functions of the pd780816 subseries. organization the pd780816 subseries manual is separated into two parts: this manual and the instruction edition (common to the 78k/0 series). pd780816 78k/0 series subseries user?s manual this manual instruction pin functions cpu functions internal block functions instruction set interrupt explanation of each instruction other on-chip peripheral functions how to read this manual before reading this manual, you should have general knowledge of electric and logic circuits and microcontrollers. when using this manual as the manual for (a) products, (a1) products, and (a2) products: o only the quality grade differs between (a), (a1) and (a2) products. read the part number as follows: pd780814 o pd780814(a), pd780814(a1), pd780814(a2) pd780816 o pd780816(a), pd780816(a1), pd780816(a2) pd78f0818 o pd78f0818(a) when you want to understand the function in general: o read this manual in the order of the contents. how to interpret the register format: o for the bit number enclosed in square, the bit name is defined as a reserved word in ra78k/0, and in cc78k/0 and defined in the header file of hte iar compiler. to make sure the details of the registers when you know the register name. o refer to appendix c. 6 preface user?s manual u15251ee4v0ud00 related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. related documents for pd780816 subseries related documents for development tools (user's manuals) document name document no. japanese english pd780816 subseries user?s manual planned this manual 78k/0 series user?s manual-instruction u12326j u12326e 78k/0 series instruction table u10903j - 78k/0 series instruction set u10904j u12326e pd780816 subseries special function register table - - document name document no. japanese english ra78k series assembler package operation eeu-809 eeu-1399 language eeu-815 eeu-1404 ra78k series structured assembler preprocessor eeu-817 eeu-1402 cc78k series c compiler operation eeu-656 eeu-1280 language eeu-655 eeu-1284 cc78k/0 c compiler operation u11517j - language u11518j - cc78k/0 c compiler application no te programming note eea-618 eea-1208 cc78k series library source file eeu-777 - ie-78k0-ns-a u14889j u14889e ie-78k0-ns-p04 u14514j u14514e ie-780818-ns-em4 u14514j u14514e np-64gk -- sm78k0 system simulator windows? base reference u15373j u15373e sm78k0 series system simulator external part user open interface u15802j u15802e id78k0-ns integrated debugger u15185j u15185e 7 preface user?s manual u15251ee4v0ud00 related documents for embedded software (user?s manual) other documents caution: the above documents are subject to change without prior notice. be sure to use the latest version document when starting design. document name document no. japanese english 78k/0 series real-time os basics u11537j - installation u11536j - technical u11538j - 78k/0 series os mx78k0 basics eeu-5010 - fuzzy knowledge data creation tool eeu-829 eeu1438 78k/0, 78k/ii, 87ad series fuzzy in ference development support sys- tem-translator eeu-862 eeu-1444 78k/0 series fuzzy inference de velopment support system- fuzzy inference module eeu-858 eeu-1441 78k/0 series fuzzy inference de velopment support system- fuzzy inference debugger eeu-921 eeu-1458 document name document no. japanese english ic package manual c10943x iei-1213 semiconductor device mounting technology manual c10535j c10535e quality grade on nec semiconductor devices c11531j c11531e reliability quality control on nec semiconductor devices c10983j c10983e electric static discharge (esd) test mem-539 - semiconductor devices quality assurance guide mei-603 mei-1202 microcontroller related product gui de - third party manufacturers u11416j - 8 preface user?s manual u15251ee4v0ud00 legend symbols and notation are used as follows: weight in data notation : left is high-order column, right is low order column active low notation : xxx (pin or signal name is over-scored) or /xxx (slash before signal name) memory map address: : high order at high stage and low order at low stage note : explanation of (note) in the text caution : item deserving extra attention remark : supplementary explanation to the text numeric notation : binary . . . xxxx or xxx b decimal . . . xxxx hexadecimal . . . xxxx h or 0x xxxx prefixes representing powers of 2 (address space, memory capacity) k (kilo): 2 10 = 1024 m (mega): 2 20 = 1024 2 = 1,048,576 g (giga): 2 30 = 1024 3 = 1,073,741,824 9 user?s manual u15251ee4v0ud00 table of contents preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 chapter 1 outline (pd780816 subseries) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.2 application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.3 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.4 quality grade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 1.5 pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.6 78k/0 can products expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.7 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 1.8 overview of functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.9 differences between flash and mask rom version . . . . . . . . . . . . . . . . . . . . . . . . . . 33 chapter 2 pin function (pd780816 subseries) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.1 pin function list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 2.2 non-port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 2.3 description of pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.3.1 p00 to p03 (port 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.3.2 p10 to p17 (port 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.3.3 p20 to p27 (port 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.3.4 p40 to p47 (port 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.3.5 p50 to p57 (port 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.3.6 p60 to p65 (port 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.3.7 p70, p71 (port 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.3.8 ctxd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.3.9 crxd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.3.10 cclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.3.11 ani0 to ani11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.3.12 av dd /av ref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.3.13 av ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.3.14 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.3.15 x1 and x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.3.16 cl1 and cl2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.3.17 v dd0 , v dd1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.3.18 v ss0 , v ss1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.3.19 v pp (pd78f0818 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.3.20 ic (mask rom version only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.4 pin i/o circuits and recommended connection of unused pins . . . . . . . . . . . . . . . 43 chapter 3 cpu architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.1 memory space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.1.1 internal program memory space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.1.2 internal data memory space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.1.3 special function register (sfr) area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.1.4 data memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.2 processor registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.2.1 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.2.2 general registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.2.3 special function register (sfr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.3 instruction address addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.3.1 relative addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.3.2 immediate addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.3.3 table indirect addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.3.4 register addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.4 operand address addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10 user?s manual u15251ee4v0ud00 3.4.1 implied addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.4.2 register addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.4.3 direct addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.4.4 short direct addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.4.5 special function register (sfr) addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.4.6 register indirect addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.4.7 based addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.4.8 based indexed addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.4.9 stack addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 chapter 4 port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.1 port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 4.2 port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 9 4.2.1 port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.2.2 port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.2.3 port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.2.4 port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.2.5 port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.2.6 port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.2.7 port 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.3 port function control registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.4 port function operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.4.1 writing to input/output port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.4.2 reading from input/output port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.4.3 operations on input/output port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 chapter 5 clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 5.1 clock generator functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 5.2 clock generator configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.3 clock generator control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.4 system clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.4.1 main system clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.4.2 subsystem clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.4.3 when no subsystem clock is used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.5 clock generator operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5.5.1 main system clock operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.5.2 subsystem clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.6 changing system clock and cpu clock settings . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.6.1 time required for switchover between system clock and cpu clock . . . . . . . . 104 5.6.2 system clock and cpu clock switching procedure . . . . . . . . . . . . . . . . . . . . . . 105 chapter 6 main clock monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.1 main clock monitor function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.2 main clock monitor circuit configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.3 main clock monitor control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.4 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 chapter 7 16-bit timer 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 7.1 16-bit timer/event counter function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 7.2 16-bit timer/event counter 0 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 7.3 16-bit timer/event counter 0 control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 7.4 16-bit timer/event counter 0 operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 7.4.1 operation as interval timer (16 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 7.4.2 ppg output operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 7.4.3 pulse width measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 7.4.4 operation as external event counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7.4.5 operation to output square wave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 7.5 16-bit timer/event counter 0 operating precautions . . . . . . . . . . . . . . . . . . . . . . . 137 11 user?s manual u15251ee4v0ud00 chapter 8 16-bit timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 8.1 16-bit timer 2 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 8.2 16-bit timer 2 configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 8.3 16-bit timer 2 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 8.4 16-bit timer 2 operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 8.4.1 pulse width measurement operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 8.5 16-bit timer 2 precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 chapter 9 8-bit timer/event counters 50 and 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 9.1 8-bit timer/event counters 50 and 51 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 9.1.1 8-bit operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 9.1.2 16-bit operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 9.2 8-bit timer/event counters 50 and 51 configurations. . . . . . . . . . . . . . . . . . . . . . . 155 9.3 8-bit timer/event counters 50 and 51 control registers . . . . . . . . . . . . . . . . . . . . 158 9.4 8-bit timer/event counters 50 and 51 operations . . . . . . . . . . . . . . . . . . . . . . . . . . 163 9.4.1 interval timer operations (8-bit timer/event counter mode) . . . . . . . . . . . . . . . . 163 9.4.2 external event counter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 9.4.3 square-wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 9.4.4 pwm output operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 9.5 operation as interval timer (16-bit operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 9.6 cautions on 8-bit timer/event counters 50 and 51 . . . . . . . . . . . . . . . . . . . . . . . . . 178 chapter 10 watch timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 10.1 watch timer functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 10.2 watch timer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 10.3 watch timer mode register (wtm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 10.4 watch timer operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 10.4.1 watch timer operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 10.4.2 interval timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 chapter 11 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 11.1 watchdog timer functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 11.2 watchdog timer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 11.3 watchdog timer control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 11.4 watchdog timer operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 11.4.1 watchdog timer operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 11.4.2 interval timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 chapter 12 clock output control circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 12.1 clock output control circuit functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 12.2 clock output control circuit configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 12.3 clock output function control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 chapter 13 a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 13.1 a/d converter functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 13.2 a/d converter configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 13.3 a/d converter control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 13.4 a/d converter operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 13.4.1 basic operations of a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 13.4.2 input voltage and conversion results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 13.4.3 a/d converter operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 13.5 a/d converter precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 13.6 cautions on emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 13.6.1 d/a converter mode register (dam0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 chapter 14 serial interface sio20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 14.1 serial interface sio20 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 14.2 serial interface sio20 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 12 user?s manual u15251ee4v0ud00 14.3 serial interface sio20 list of sfrs (speci al function registers) . . . . . . . . . . . . . 220 14.4 serial interface control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 14.5 operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 14.5.1 operation stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 14.5.2 3-wire serial i/o mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 chapter 15 serial interface sio30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 15.1 sio30 functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 35 15.2 sio30 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 15.3 list of sfrs (special function registers). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 15.4 serial interface control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 15.5 serial interface operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 15.5.1 operation stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 15.5.2 three-wire serial i/o mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 15.5.3 two-wire serial i/o mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 chapter 16 serial interface channel uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 16.1 uart functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 16.2 uart configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 16.3 list of sfrs (special function registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 16.4 serial interface control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 16.5 serial interface operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 16.5.1 operation stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 16.5.2 asynchronous serial interface (uart) mode . . . . . . . . . . . . . . . . . . . . . . . . . . 256 16.6 standby function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8 chapter 17 can controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 17.1 can protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270 17.1.1 protocol mode function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 17.1.2 message format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 17.1.3 data frame / remote frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 17.1.4 description of each field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 17.1.5 error frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 17.1.6 overload frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 17.2 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 17.2.1 arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 17.2.2 bit stuffing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 17.2.3 multi master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 17.2.4 multi cast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 17.2.5 sleep mode/stop function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 17.2.6 error control function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 17.2.7 baud rate control function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 17.2.8 state shift chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 17.3 outline description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1 17.4 connection with target system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 17.5 can controller configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 17.6 special function register for can- module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 17.7 message and buffer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 17.8 transmit buffer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 17.9 transmit message format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 17.10 receive buffer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 17.11 receive message format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 17.12 mask function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306 17.13 operation of the can controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 17.13.1 can control register (canc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 17.13.2 dcan error status register (canes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 17.13.3 can transmit error counter (tec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 17.13.4 can receive error counter (rec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 13 user?s manual u15251ee4v0ud00 17.13.5 message count register (mcnt). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 17.14 baudrate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 17.15 function control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 17.15.1 transmit control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 17.15.2 receive control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 17.15.3 mask control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 17.15.4 special functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 17.16 interrupt information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4 17.16.1 interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 17.16.2 transmit interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 17.16.3 receive interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 17.16.4 error interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 17.17 influence of the standby function of the can controller . . . . . . . . . . . . . . . . . . . . 336 17.17.1 cpu halt mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 17.17.2 cpu stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 17.17.3 dcan sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 17.17.4 dcan stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 17.18 functional description by flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 17.18.1 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 17.18.2 transmit preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 17.18.3 abort transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 17.18.4 handling by the dcan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 17.18.5 receive event oriented . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 17.18.6 receive task oriented . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 17.19 can controller precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 chapter 18 interrupt functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 18.1 interrupt function types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 18.2 interrupt sources and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 18.3 interrupt function control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 18.4 interrupt servicing operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 18.4.1 non-maskable interrupt request acknowledge operation . . . . . . . . . . . . . . . . . 357 18.4.2 maskable interrupt request acknowledge operation . . . . . . . . . . . . . . . . . . . . . 359 18.4.3 software interrupt request acknowledge operation . . . . . . . . . . . . . . . . . . . . . 362 18.4.4 multiple interrupt servicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 18.4.5 interrupt request reserve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 chapter 19 key return mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 19.1 key return mode functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 19.2 key return mode circuit configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 19.3 key return mode control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 chapter 20 standby function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 20.1 standby function and configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 20.1.1 standby function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 20.1.2 standby function control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 20.2 standby function operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 20.2.1 halt mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 20.2.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 chapter 21 reset function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 21.1 reset function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 chapter 22 pd78f0818 and memory definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 22.1 memory size switching register (ims) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 22.2 internal expansion ram size switching register . . . . . . . . . . . . . . . . . . . . . . . . . . 387 22.3 self-programming and oscillation control register . . . . . . . . . . . . . . . . . . . . . . . . 388 22.4 flash memory programming with flash programmer. . . . . . . . . . . . . . . . . . . . . . . . 389 14 user?s manual u15251ee4v0ud00 22.4.1 selection of transmission method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 22.4.2 initialization of the programming mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 22.4.3 flash memory programming function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 22.4.4 flash programmer connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 22.4.5 flash programming precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 22.5 flash self-programming control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 22.5.1 flash self-programming mode control register (flpmc) . . . . . . . . . . . . . . . . . 393 chapter 23 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 23.1 legends used in operation list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 23.1.1 operand identifiers and description methods . . . . . . . . . . . . . . . . . . . . . . . . . . 395 23.1.2 description of ?operation? column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 23.2 operation list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397 23.3 instructions listed by addressing type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 chapter 24 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 24.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 24.2 capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .412 24.3 main system clock oscillation circuit characteristics . . . . . . . . . . . . . . . . . . . . . . 413 24.4 subsystem clock oscillation circuit characteristics . . . . . . . . . . . . . . . . . . . . . . . 416 24.5 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9 24.6 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6 24.6.1 basic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 24.6.2 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 24.6.3 a/d converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 24.6.4 data memory stop mode low supply voltage data retention characteristics 442 24.6.5 flash memory programming characteristics: pd78f0818(a) . . . . . . . . . . . . 445 chapter 25 package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 chapter 26 recommended soldering conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 appendix a development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 appendix b embedded software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 appendix c register index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 appendix d revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 15 user?s manual u15251ee4v0ud00 list of figures figure 1-1: pin configuration ................................................................................................... ...... 27 figure 1-2: 78k/0 can products expansion ................................................................................. 29 figure 1-3: block diagram ....................................................................................................... ...... 31 figure 2-1: connection of ic pins............................................................................................... ... 42 figure 2-2: pin input/output circuits ........................................................................................... .. 45 figure 3-1: memory map 0f the pd780814 ................................................................................. 47 figure 3-2: memory map of the pd780816 ................................................................................. 48 figure 3-3: memory map of the pd78f0818 ............................................................................... 49 figure 3-4: data memory addressing of pd780814 .................................................................... 54 figure 3-5: data memory addressing of pd780816 .................................................................... 55 figure 3-6: data memory addressing of pd78f0818.................................................................. 56 figure 3-7: program counter configuration .................................................................................. 57 figure 3-8: program status word configuration ........................................................................... 57 figure 3-9: stack pointer configuration......................................................................................... 59 figure 3-10: data to be saved to stack memory............................................................................. 59 figure 3-11: data to be reset to stack memory ............................................................................. 59 figure 3-12: general register configuration ................................................................................... 60 figure 3-13: relative addressing ................................................................................................ .... 65 figure 3-14: immediate addressing............................................................................................... .. 66 figure 3-15: table indirect addressing.......................................................................................... .. 67 figure 3-16: register addressing ................................................................................................ .... 68 figure 3-17: register addressing ................................................................................................ .... 70 figure 3-18: direct addressing .................................................................................................. ...... 71 figure 3-19: short direct addressing ............................................................................................ ... 72 figure 3-20: special-function register (sfr) addressing.............................................................. 73 figure 3-21: register indirect addressing ....................................................................................... .74 figure 3-22: based addressing description example....................................................................... 75 figure 3-23: based indexed addressing description example ......................................................... 76 figure 3-24: stack addressing description example ........................................................................ 76 figure 4-1: port types .......................................................................................................... ......... 77 figure 4-2: p00 to p03 configurations .......................................................................................... 8 0 figure 4-3: p10 to p17 configurations .......................................................................................... 8 1 figure 4-4: p20 to p27 configurations .......................................................................................... 8 2 figure 4-5: p40 to p47 configurations .......................................................................................... 8 3 figure 4-6: block diagram of fa lling edge detection circuit........... .............................................. 83 figure 4-7: p50 to p57 configurations .......................................................................................... 8 4 figure 4-8: p60 to p67 configurations .......................................................................................... 8 5 figure 4-9: p70, p71 configurations ............................................................................................. 86 figure 4-10: port mode register format ......................................................................................... 8 8 figure 4-11: pull-up resistor option register (pu0, pu2, pu4 to pu7) format............................ 89 figure 4-12: port function register (pf2) format .......................................................................... 90 figure 4-13: key return mode register (krm) format .................................................................. 91 figure 5-1: block diagram of clock generator .............................................................................. 94 figure 5-2: processor clock control register format (1/2) .......................................................... 95 figure 5-3: external circuit of main system clock oscillator ...... .................................................. 97 figure 5-4: external circuit of subsystem clock oscillator ........................................................... 98 figure 5-5: examples of oscillato r with bad connection (1/3) ........ .............................................. 99 figure 5-6: main system clock stop function ............................................................................ 103 figure 5-7: system clock and cpu clock switching................................................................... 105 figure 6-1: main clock monitor circuit block diagram ................................................................ 108 figure 6-2: format clock monitor mode register (clm)............................................................. 109 figure 7-1: block diagram of 16-bit timer/event counter 0 (tm0) ............................................. 112 figure 7-2: format of 16-bit timer mode control register (tmc0) ............................................ 117 figure 7-3: format of capture/ compare control register 0 (crc0 ) .......................................... 118 figure 7-4: format of 16-bit timer output control register (toc0)........................................... 119 16 user?s manual u15251ee4v0ud00 figure 7-5: format of prescaler mode register 0 (prm0) .......................................................... 120 figure 7-6: port mode register 7 (pm7) format ......................................................................... 121 figure 7-7: control register settings when timer 0 operates as interval timer ....................... 122 figure 7-8: configuration of interval timer .................................................................................. 123 figure 7-9: timing of interval timer operation ............................................................................ 123 figure 7-10: control register settings in ppg output operation.................................................. 124 figure 7-11: control register settings for pulse width measurement with free running counter and one capture register............................................. 125 figure 7-12: configuration for pulse width measurement with free running counter................. 126 figure 7-13: timing of pulse width measurement with free running counter and one capture register (with both edges specified)............................................. 126 figure 7-14: control register settings for measurement of two pulse widths with free running counter........................................................................................ 127 figure 7-15: cr01 capture operation with rising edge specified ............................................... 128 figure 7-16: timing of pulse width measurement operation with free running counter (with both edges specified)........................................................................................ 128 figure 7-17: control register settings for pulse width measurement with free running counter and two capture registers........................................... 129 figure 7-18: timing of pulse width measurement with free running counter and two capture registers (with rising edge specified) ........................................... 130 figure 7-19: control register settings for pulse width measurement by restarting .................... 131 figure 7-20: timing of pulse width measurement by restarting (with rising edge specified)....... 132 figure 7-21: control register settings in external event counter mode....................................... 133 figure 7-22: configuration of external event counter ................................................................... 134 figure 7-23: timing of external event counter operation (with rising edge specified) ................. 134 figure 7-24: set contents of control registers in square wave output mode............................. 135 figure 7-25: timing of square wave output operation ................................................................ 136 figure 7-26: start timing of 16-bit timer register ........................................................................ 137 figure 7-27: timing after changing compare register during timer count operation ................ 137 figure 7-28: data hold timing of capture register....................................................................... 138 figure 7-29: operation timing of ovf0 flag................................................................................. 139 figure 8-1: timer 2 block diagram .............................................................................................. 1 41 figure 8-2: 16-bit timer mode control register (tmc2) format ................................................ 143 figure 8-3: capture pulse control register (crc2) format ....................................................... 144 figure 8-4: prescaler mode register (prm2) format ................................................................. 145 figure 8-5: configuration diagram for pulse width measurement by using the free running counter ......................................................................................... 146 figure 8-6: timing of pulse width measurement operation by using the free running counter and one capture register (with both edges specified)147 figure 8-7: cr2m capture operation with rising edge specified .............................................. 148 figure 8-8: timing of pulse width measurement operation by free running counter (with both edges specified) ...................................................................................... 148 figure 8-9: 16-bit timer register start timing ............................................................................ 149 figure 8-10: capture register data retention timing................................................................... 149 figure 9-1: 8-bit timer/event counter 50 block diagram............................................................ 155 figure 9-2: 8-bit timer/event counter 51 block diagram............................................................ 156 figure 9-3: block diagram of 8-bit timer/event coun ters 50 and 51 output control circuit ...... 156 figure 9-4: timer clock select register 50 format..................................................................... 158 figure 9-5: timer clock select register 51 format..................................................................... 159 figure 9-6: 8-bit timer mode control register 50 format........................................................... 160 figure 9-7: 8-bit timer mode control register 51 format (1/2) .................................................. 161 figure 9-8: port mode register 2 format .................................................................................... 162 figure 9-9: 8-bit timer mode control register settings for interval timer operation ................. 163 figure 9-10: interval timer operation timings (1/3)...................................................................... 164 figure 9-11: 8-bit timer mode control register setting for external event counter operation.... 168 figure 9-12: external event counter operation timings (with rising edge specified) ................. 168 figure 9-13: 8-bit timer mode control register settings for square-wave output operation ..... 169 figure 9-14: square-wave output operation timing ..................................................................... 170 17 user?s manual u15251ee4v0ud00 figure 9-15: 8-bit timer control register settings for pwm output operation ............................ 171 figure 9-16: pwm output operation timing (active high setting)................................................. 172 figure 9-17: pwm output operation timings (crn0 = 00h, active high setting) ......................... 172 figure 9-18: pwm output operation timings (crn = ffh, active high setting) ........................... 173 figure 9-19: pwm output operation timings (crn changing, active high setting)....................... 173 figure 9-20: 8-bit timer mode control register settings for 16-bit interval timer operation....... 174 figure 9-21: 16-bit resolution cascade mode (with tm50 and tm51)......................................... 176 figure 9-22: 8-bit timer registers 50 and 51 start timings .......................................................... 178 figure 9-23: external event counter operation timings ............................................................... 178 figure 9-24: timings after compare register change during timer count operation ................. 179 figure 10-1: block diagram of watch timer.................................................................................. 181 figure 10-2: watch timer mode control register (wtm) format (1/2) ........................................ 184 figure 10-3: operation timing of watch timer/interval timer....................................................... 188 figure 11-1: watchdog timer block diagram................................................................................ 191 figure 11-2: timer clock select register 2 format....................................................................... 192 figure 11-3: watchdog timer mode register format ................................................................... 193 figure 12-1: remote controlled output application example ....................................................... 197 figure 12-2: clock output control circuit block diagram.............................................................. 198 figure 12-3: clock output selection register (cks) format ........................................................ 199 figure 12-4: port mode register 2 format .................................................................................... 200 figure 13-1: a/d converter block diagram ................................................................................... 201 figure 13-2: power-fail detection function block diagram .......................................................... 202 figure 13-3: a/d converter mode register (adm1) format.......................................................... 204 figure 13-4: analog input channel specification register (ads1) format ................................... 205 figure 13-5: power-fail compare mode register (pfm) format.................................................. 206 figure 13-6: power-fail compare threshold value register (pft) ................................................... 206 figure 13-7: basic operation of 8-bit a/d converter..................................................................... 208 figure 13-8: relation between analog input voltage and a/d conversion result ........................ 210 figure 13-9: a/d conversion ..................................................................................................... .... 212 figure 13-10: example method of reducing current consumption in standby mode .................... 213 figure 13-11: analog input pin handling ......................................................................................... 214 figure 13-12: a/d conversion end interrupt request generation timing....................................... 215 figure 13-13: d/a converter mode register (dam0) format.......................................................... 216 figure 14-1: block diagram of sio20 ............................................................................................ 2 18 figure 14-2: serial operation mode register (csim20) format (1/2) ........................................... 221 figure 14-3: serial transfer operation timing according to clpo and clph settings ............... 223 figure 14-4: receive data buffer status register (srbs20) format ........................................... 224 figure 14-5: serial i/f data buffer register (sirb20) ..................................................................... 224 figure 14-6: format of serial operation mode register (csim20) ............................................... 225 figure 14-7: serial operation mode register (csim20) format ................................................... 226 figure 14-8: serial transfer operation timing according to clpo and clph settings ............... 227 figure 14-9: receive data buffer status register (srbs20) format ........................................... 228 figure 14-10: serial i/f data buffer register (sirb20) ..................................................................... 228 figure 14-11: transmission protocol for clph = 0 ......................................................................... 230 figure 14-12: transmission format for clph = 1 ............................................................................ 231 figure 14-13: overflow error conditions ......................................................................................... .232 figure 15-1: block diagram of sio30 ............................................................................................ 2 36 figure 15-2: format of serial operation mode register (csim30) ............................................... 238 figure 15-3: format of serial mode switch register (sioswi)..................................................... 239 figure 15-4: format of serial operation mode register (csim30) ............................................... 240 figure 15-5: format of serial operation mode register (csim30) ............................................... 241 figure 15-6: format of serial mode switch register (sioswi)..................................................... 242 figure 15-7: format of serial operation mode register (csim30) ............................................... 243 figure 15-8: format of serial mode switch register (sioswi)..................................................... 244 figure 15-9: timing of three-wire serial i/o mode........................................................................ 245 figure 15-10: timing of two-wire serial i/o mode .......................................................................... 245 figure 16-1: block diagram of uart ............................................................................................ 24 7 figure 16-2: format of asynchronous serial interface mode register (asim0) (1/2) ................... 250 18 user?s manual u15251ee4v0ud00 figure 16-3: format of asynchronous serial interface status register (asis0) ........................... 252 figure 16-4: format of baud rate generator control register (brgc0) (1/2)............................. 253 figure 16-5: register settings .................................................................................................. ..... 255 figure 16-6: format of asynchronous serial interface mode register (asim0) (1/2) ................... 256 figure 16-7: format of asynchronous serial interface status register (asis0) ........................... 258 figure 16-8: format of baud rate generator control register (brgc0) (1/2)............................. 259 figure 16-9: error tolerance (when k = 0), including sampling errors.......................................... 262 figure 16-10: format of transmit/receive data in asynchronous serial interface......................... 263 figure 16-11: timing of asynchronous serial interface transmit completion interrupt .................. 265 figure 16-12: timing of asynchronous serial interface receive completion interrupt ................... 266 figure 16-13: receive error timing.............................................................................................. ... 267 figure 17-1: data frame......................................................................................................... ....... 271 figure 17-2: remote frame....................................................................................................... .... 271 figure 17-3: data frame......................................................................................................... ....... 272 figure 17-4: arbitration field/standard format mode ................................................................... 272 figure 17-5: arbitration field/extended format mode................................................................... 273 figure 17-6: control field (standard format mode)...................................................................... 274 figure 17-7: control field (extended format mode) ..................................................................... 274 figure 17-8: data field ......................................................................................................... ......... 275 figure 17-9: crc field .......................................................................................................... ........ 275 figure 17-10: ack field ......................................................................................................... ......... 276 figure 17-11: end of frame...................................................................................................... ....... 276 figure 17-12: interframe space/error active ................................................................................... 27 7 figure 17-13: interframe space/error passive ................................................................................ 277 figure 17-14: error frame ....................................................................................................... ........ 278 figure 17-15: overload frame.................................................................................................... ..... 279 figure 17-16: nominal bit time (8 to 25 time quanta) ................................................................... 285 figure 17-17: adjusting synchronization of the data bit ................................................................. 286 figure 17-18: bit synchronization............................................................................................... ..... 287 figure 17-19: transmission state shift chart.................................................................................. 28 8 figure 17-20: reception state shift chart ....................................................................................... 289 figure 17-21: error state shift chart ........................................................................................... .... 290 figure 17-22: structural block diagram.......................................................................................... .291 figure 17-23: connection to the can bus....................................................................................... 29 2 figure 17-24: transmit message definition bits ............................................................................. 296 figure 17-25: transmit identifier .............................................................................................. ....... 297 figure 17-26: transmit data .................................................................................................... ....... 298 figure 17-27: control bits for receive identifier ............................................................................. 3 01 figure 17-28: receive status bits (1/2) ........................................................................................ .. 302 figure 17-29: receive identifier ............................................................................................... ....... 304 figure 17-30: receive data ..................................................................................................... ....... 305 figure 17-31: identifier compare with mask .................................................................................... 30 7 figure 17-32: control bits for mask identifier ................................................................................. 308 figure 17-33: mask identifier .................................................................................................. ........ 309 figure 17-34: can control register (1/2) ....................................................................................... 310 figure 17-35: dcan support...................................................................................................... ..... 311 figure 17-36: time stamp function ............................................................................................... .313 figure 17-37: sofout toggle function......................................................................................... 313 figure 17-38: global time system function ................................................................................... 313 figure 17-39: can error status register (1/3) ............................................................................... 314 figure 17-40: transmit error counter ........................................................................................... .. 317 figure 17-41: receive error counter ............................................................................................ .. 317 figure 17-42: message count register (mcnt) (1/2) .................................................................... 318 figure 17-43: bit rate prescaler (1/2) ......................................................................................... ... 320 figure 17-44: synchronization control registers 0 and 1 (1/2) ..................................................... 322 figure 17-45: transmit control register (1/2) ................................................................................ 32 6 figure 17-46: receive message register ....................................................................................... 32 8 figure 17-47: mask control register (1/2) ...................................................................................... 329 19 user?s manual u15251ee4v0ud00 figure 17-48: redefinition control register (1/2) ........................................................................... 332 figure 17-49: initialization flow chart ......................................................................................... .... 339 figure 17-50: transmit preparation .............................................................................................. ... 340 figure 17-51: transmit abort .................................................................................................... ....... 341 figure 17-52: handling of semaphore bits by dcan-module......................................................... 342 figure 17-53: receive with interrupt, software flow ....................................................................... 343 figure 17-54: receive, software polling ......................................................................................... 344 figure 18-1: basic configuration of interrupt function (1/2).......................................................... 349 figure 18-2: interrupt request flag register format .................................................................... 352 figure 18-3: interrupt mask flag register format......................................................................... 353 figure 18-4: priority specify flag register format........................................................................ 354 figure 18-5: formats of external interrupt rising edge enable register and external interrup t falling edge enable register ................................................ 355 figure 18-6: program status word format ................................................................................... 356 figure 18-7: flowchart from non-maskable interrupt generation to acknowledge ...................... 357 figure 18-8: non-maskable interrupt request acknowledge timing ............................................ 358 figure 18-9: non-maskable interrupt request acknowledge operation ....................................... 358 figure 18-10: interrupt request acknowledge processing algorithm ............................................. 360 figure 18-11: interrupt request acknowledge timing (minimum time).......................................... 361 figure 18-12: interrupt request acknowledge timing (maximum time)......................................... 361 figure 18-13: multiple interrupt example (1/2) ................................................................................ 36 4 figure 18-14: interrupt request hold ............................................................................................ .. 367 figure 19-1: key return mode circuit block diagram ................................................................... 369 figure 19-2: key return mode register (krm) format ................................................................ 370 figure 19-3: port mode register 4 (pm4) format ......................................................................... 371 figure 20-1: oscillation stabilization time select register (osts) format.. ................................ 374 figure 20-2: standby timing ..................................................................................................... .... 374 figure 20-3: halt mode clear upon interrupt generation ........................................................... 376 figure 20-4: halt mo de release by reset input ...................................................................... 377 figure 20-5: stop mode release by interrupt generation .......................................................... 379 figure 20-6: release by stop mode reset input...................................................................... 380 figure 21-1: block diagram of reset function .............................................................................. 381 figure 21-2: timing of reset input by reset input ..................................................................... 382 figure 21-3: timing of reset due to watchdog timer overflow.................................................... 382 figure 21-4: timing of reset input in stop mode by reset input ............................................. 382 figure 22-1: memory size switching register format .................................................................. 386 figure 22-2: internal expansion ram size switching register (ixs) format ............................... 387 figure 22-3: self-programmi ng and oscillation control register (spoc) format ........................ 388 figure 22-4: transmission method selection format .................................................................... 389 figure 22-5: connection of using the 3-wire sio30 method ......................................................... 391 figure 22-6: connection of using the uart method ..................................................................... 392 figure 22-7: flash self-programming mode control register format .......................................... 393 figure a-1: development tool configuration ............................................................................... 454 20 user?s manual u15251ee4v0ud00 21 user?s manual u15251ee4v0ud00 list of tables table 1-1: the major functional differences between the subseries ............................................... 30 table 1-2: overview of functions ................................................................................................ .... 32 table 1-3: differences between flash and mask rom version ...................................................... 33 table 2-1: pin input/output types............................................................................................... .... 35 table 2-2: non-port pins ........................................................................................................ ......... 36 table 2-3: types of pin input/output circuits.................................................................................. 4 3 table 3-1: internal rom capacities .............................................................................................. .. 50 table 3-2: vectored interrupts .................................................................................................. ....... 51 table 3-3: internal high-speed ram.............................................................................................. .. 53 table 3-4: internal expansion ram (including sharing with dcan) ................................................ 53 table 3-5: special function register list ....................................................................................... .62 table 3-6: implied addressing ................................................................................................... ...... 69 table 3-7: register addressing .................................................................................................. ..... 70 table 3-8: direct addressing.................................................................................................... ........ 71 table 3-9: short direct addressing.............................................................................................. ..... 72 table 3-10: special-function register (sfr) addressing................................................................. 73 table 3-11: register indirect addressing ........................................................................................ ... 74 table 3-12: based addressing.................................................................................................... ....... 75 table 3-13: based indexed addressing ............................................................................................ .76 table 4-1: pin input/output types............................................................................................... .... 78 table 4-2: port configuration................................................................................................... ........ 79 table 5-1: clock generator configuration ....................................................................................... 9 4 table 5-2: maximum time required for cpu clock switchover ................................................... 104 table 6-1: main clock monitor configuration ................................................................................ 108 table 7-1: configuration of 16-bit timer/event counter (tm0) ..................................................... 112 table 7-2: valid edge of ti00 pin and valid edge of capture trigger of capture/compare register. 114 table 7-3: valid edge of ti01 pin and valid edge of capture trigger of capture/compare register. 114 table 8-1: timer 2 configuration ................................................................................................ ... 142 table 9-1: 8-bit timer/event counter 50 interval times ............................................................... 152 table 9-2: 8-bit timer/event counter 51 interval times ............................................................... 152 table 9-3: 8-bit timer/event counter 50 square-wave output ranges....................................... 153 table 9-4: 8-bit timer/event counter 51 square-wave output ranges....................................... 153 table 9-5: 16-bit timer/event counter tm50/tm51 interval times .............................................. 154 table 9-6: 16-bit timer/event counter tm50/tm51 square-wave output ranges ..................... 154 table 9-7: 8-bit timer/event counters 50 and 51 configurations ................................................. 155 table 9-8: 8-bit timer/event counters 50 interval times.............................................................. 167 table 9-9: 8-bit timer/event counters 51 interval times.............................................................. 167 table 9-10: 8-bit timer/event counters 50 square-wave output ranges (8-bit timer/event counter mode)................................................................................ 170 table 9-11: 8-bit timer/event counters 51 square-wave output ranges (8-bit timer/event counter mode)................................................................................ 170 table 9-12: 8-bit timer/event counters interval ti mes (16-bit timer/event counter mode).......... 177 table 9-13: 8-bit timer/event counter square-wave output ranges (16-bit timer/event counter mode).............................................................................. 177 table 10-1: watch timer interval time ........................................................................................... 182 table 10-2: interval timer interval time........................................................................................ .. 182 table 10-3: watch timer configuration........................................................................................... 183 table 10-4: watch timer operation ............................................................................................... .186 table 10-5: interval timer operation............................................................................................ ... 187 table 11-1: watchdog timer inadvertent program overrun detection times ................................ 189 table 11-2: interval times ...................................................................................................... ......... 190 table 11-3: watchdog timer configuration..................................................................................... 191 table 11-4: watchdog timer overrun detection time .................................................................... 194 table 11-5: interval timer interval time........................................................................................ .. 195 table 12-1: clock output control circuit configuration................................................................... 198 22 user?s manual u15251ee4v0ud00 table 13-1: a/d converter configuration ........................................................................................ 2 02 table 14-1: configuration of sio20 .............................................................................................. ... 219 table 14-2: list of sfrs (special function registers) ................................................................... 220 table 15-1: composition of sio30 ................................................................................................ .. 237 table 15-2: list of sfrs (special function registers).................................................................... 237 table 15-3: operating modes and start trigger .............................................................................. 239 table 15-4: operating modes and start trigger .............................................................................. 242 table 15-5: operating modes and start trigger .............................................................................. 244 table 16-1: configuration of uart ............................................................................................... .. 248 table 16-2: list of sfrs (special function registers).................................................................... 249 table 16-3: relation between 5-bit counter?s source clock and ?n? value .................................... 261 table 16-4: relation between main system clock and baud rate ................................................. 262 table 16-5: causes of receive errors............................................................................................ .267 table 17-1: outline of the function ............................................................................................. .... 269 table 17-2: bit number of the identifier ....................................................................................... ... 273 table 17-3: rtr setting ........................................................................................................ ......... 273 table 17-4: mode setting ....................................................................................................... ........ 273 table 17-5: data length code setting ........................................................................................... 274 table 17-6: operation in the error state ....................................................................................... .. 277 table 17-7: definition of each field ........................................................................................... ..... 278 table 17-8: definition of each frame ........................................................................................... .. 279 table 17-9: arbitration ........................................................................................................ ............ 280 table 17-10: bit stuffing ...................................................................................................... ............. 280 table 17-11: error types ....................................................................................................... ........... 282 table 17-12: output timing of the error frame ................................................................................ 28 2 table 17-13: types of error .................................................................................................... .......... 283 table 17-14: error counter ..................................................................................................... .......... 284 table 17-15: segment name and segment length ......................................................................... 285 table 17-16: can configuration.................................................................................................. ...... 292 table 17-17: sfr definitions.................................................................................................... ......... 293 table 17-18: sfr bit definitions ................................................................................................ ....... 293 table 17-19: message and buffer configuration ............................................................................... 294 table 17-20: transmit message format............................................................................................ 295 table 17-21: receive message format............................................................................................. 300 table 17-22: mask function ...................................................................................................... ........ 306 table 17-23: possible setup of the sofout function..................................................................... 312 table 17-24: transmission / reception flag ..................................................................................... 3 12 table 17-25: possible reactions of the dcan.................................................................................. 317 table 17-26: mask operation buffers............................................................................................. ... 330 table 17-27: interrupt sources .................................................................................................. ........ 334 table 18-1: interrupt source list ............................................................................................... ...... 348 table 18-2: various flags corresponding to interrupt request sources ........................................ 351 table 18-3: times from maskable interrupt request generation to interrupt service .................... 359 table 18-4: interrupt request enabled for multiple interrupt during interrupt servicing ................. 363 table 19-1: key return mode configuration ................................................................................... 369 table 20-1: halt mode operation status ...................................................................................... 375 table 20-2: operation after halt mode release ........................................................................... 377 table 20-3: stop mode operating status...................................................................................... 378 table 20-4: operation after stop mode release........................................................................... 380 table 21-1: hardware status after reset ........................................................................................ 3 83 table 22-1: differences among pd78f0818 and mask rom versions ........................................ 385 table 22-2: values to be set after reset of the memory size switching register .......................... 386 table 22-3: examples of internal expansion ram size switching register settings ..................... 387 table 22-4: values when the internal expansion ram size switching register is reset .............. 387 table 22-5: transmission method list............................................................................................ .389 table 22-6: main functions of flash memory programming........................................................... 390 table 23-1: operand identifiers and description methods .............................................................. 395 table 23-2: operation list ...................................................................................................... ......... 397 23 user?s manual u15251ee4v0ud00 table 23-3: 8-bit instructions .................................................................................................. ......... 405 table 23-4: 16-bit instructions ................................................................................................. ........ 406 table 23-5: bit manipulation instructions....................................................................................... .. 406 table 23-6: call/instructions/branch instructions ............................................................................. 40 7 24 user?s manual u15251ee4v0ud00 25 user?s manual u15251ee4v0ud00 chapter 1 outline (pd780816 subseries) 1.1 features internal memory instruction execution time can be changed serial interface : 3 channels from high speed (0.25 s) to ultra low speed 3-wire mode : 1 channel i/o ports: 46 2-wire/3-wire mode : 1 channel 8-bit resolution a/d converter: 12 channels uart mode : 1 channel main clock monitor timer : 6 channels can-interface supply voltage : v dd = 4.0 to 5.5 v the can macro is qualified according the requirements of iso 11898 using the test procedures defined by iso 16845 and passed successfully the test procedures as recommended by c & s / fh wolfenbuettel. 1.2 application body electronics, industrial electronics, security unit etc. 1.3 ordering information remark: xxx indicates rom code suffix. item program memory (rom) data memory package part number internal high-speed ram internal expansion ram pd780814 32 kbytes 1024 bytes 480 bytes 64-pin plastic qfp (fine pitch) pd780816 48 kbytes 1024 bytes 480 bytes 64-pin plastic qfp (fine pitch) pd78f0818 59.5 kbytes 1024 bytes 2016 bytes 64-pin plastic qfp (fine pitch) part number package internal rom pd780814gk(a)-xxx-9et 64-pin plastic qfp (12 u 12 mm, resin thickness 1.2 mm) mask rom pd780814gk(a1)-xxx-9et 64-pin plastic qfp (12 u 12 mm, resin thickness 1.2 mm) mask rom pd780814gk(a2)-xxx-9et 64-pin plastic qfp (12 u 12 mm, resin thickness 1.2 mm) mask rom pd780816gk(a)-xxx-9et 64-pin plastic qfp (12 u 12 mm, resin thickness 1.2 mm) mask rom pd780816gk(a1)-xxx-9et 64-pin plastic qfp (12 u 12 mm, resin thickness 1.2 mm) mask rom pd780816gk(a2)-xxx-9et 64-pin plastic qfp (12 u 12 mm, resin thickness 1.2 mm) mask rom pd78f0818gk(a)-9et 64-pin plastic qfp (12 u 12 mm, resin thickness 1.2 mm) flash memory 26 chapter 1 outline (pd780816 subseries) user?s manual u15251ee4v0ud00 1.4 quality grade remark: xxx indicates rom code suffix. please refer to "quality grades on nec semiconductor device" (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. part number package quality grade pd780814gk(a)-xxx-9et 64-pin plastic qfp (12 u 12 mm, resin thickness 1.2 mm) special pd780814gk(a1)-xxx-9et 64-pin plastic qfp (12 u 12 mm, resin thickness 1.2 mm) special pd780814gk(a2)-xxx-9et 64-pin plastic qfp (12 u 12 mm, resin thickness 1.2 mm) special pd780816gk(a)-xxx-9et 64-pin plastic qfp (12 u 12 mm, resin thickness 1.2 mm) special pd780816gk(a1)-xxx-9et 64-pin plastic qfp (12 u 12 mm, resin thickness 1.2 mm) special pd780816gk(a2)-xxx-9et 64-pin plastic qfp (12 u 12 mm, resin thickness 1.2 mm) special pd78f0818gk(a)-9et 64-pin plastic qfp (12 u 12 mm, resin thickness 1.2 mm) special 27 chapter 1 outline (pd780816 subseries) user?s manual u15251ee4v0ud00 1.5 pin configuration (top view) 64-pin plastic qfp (12 u 12 mm) pd780814gk(a)- xxx - 9et, pd780814gk(a1)- xxx - 9et, pd780814gk(a2)- xxx - 9et pd780816gk(a)- xxx - 9et, pd780816gk(a1)- xxx - 9et, pd780816gk(a2)- xxx - 9et pd78f0818gk(a) - 9et figure 1-1: pin configuration cautions: 1. connect ic (internally connected) pin directly to v ss . 2. av dd /av ref pin should be connected to v dd . 3. av ss pin should be connected to v ss . remark: when these devices are used in applications, that require reduction of the noise, generated from inside the microcontroller, the implementation of noise reduction measures, such as connecting the v ss0 and v ss1 to different ground lines, is recommended. p56 p57 p67/si3 p66/so3/sio3 p65/sck3 p64 p63 p62/ti22 p61/ti21 p60/ti20 v dd 0 vss0 p70/ti00to0 p71/ti01 crxd ctxd p27/ti51/to51 p26/ti50/to50 p25/txd p24/rxd p23/pcl p22/sck2 p21/so2 p20/si2 avss p10/ani0 p11/ani1 p12/ani2 p13/ani3 p14/ani4 p15/ani5 p16/ani6 p41/kr1 p40/kr0 reset cl2 cl1/cclk ic/v pp x2 x1 v dd 1 vss1 ani11 ani10 ani9 ani8 av dd /av ref p17/ani7 p55 p54 p53 p52 p51 p50 p03/intp3 p02/intp2 p01/intp1 p00/intp0 p47/kr7 p46/kr6 p45/kr5 p44/kr4 p43/kr3 p42/kr2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 26 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 27 28 chapter 1 outline (pd780816 subseries) user?s manual u15251ee4v0ud00 pin identifications p00 to p03 : port 0 rxd : receive data p10 to p17 : port 1 txd : transmit data p20 to p27 : port 2 pcl : programmable clock output p40 to p47 : port 4 x1, x2 : crystal (main system clock) p50 to p57 : port 5 cl1, cl2 rc (subsystem clock) p60 to p67 : port 6 reset :reset p70, p71 : port 7 ani0 to ani11 : analog input kr0 to kr7 : key return port av ss : analog ground intp0 to intp3 : interrupt from peripherals av dd /av ref : power supply and ti00, ti01 : timer input : analog reference voltage ti50, ti51 : timer input v dd0 , v dd1 : power supply ti20 to ti22 : timer input v pp : programming power supply to00, to51, to52 : timer output v ss0 , v ss1 : ground crxd : can receive data ic : internally connected ctxd : can transmit data cclk : can clock si2, si3 : serial input so2, so3 : serial output sck2 , sck3 : serial clock sio3 : serial input/output sio3 : serial input/output 29 chapter 1 outline (pd780816 subseries) user?s manual u15251ee4v0ud00 1.6 78k/0 can products expansion the following shows the products organized according to usage. the names in the parallelograms are subseries. figure 1-2: 78k/0 can products expansion for dashboard, climate control, security units, etc., lcd 40 x 4 segments, large number of i/os: 79 78k/0 can 80-pin products in mass production products under development y subseries products are compatible with i 2 c bus. 100-pin 64-pin special assps pd780948a products 100-pin pd780828a pd780703ay pd780816a, pd780816b 80-pin pd780822b 80-pin 44-pin f-line 64-pin 78k0/ff2 78k0/fe2 78k0/fc2 for dashboard, climate control, security units, etc. on-chip automotive meter controller/driver, lcd 34 x 4 segments, lin, enhanced a/d converter, large rom up to 120 k, large number of i/os: 76 on-chip automotive meter controller/driver, lcd 28 x 4 segments for car audio application, i 2 c. specified for can controller function for automotive body applications, platform-based developments high development flexibility due to device scalability in terms of package memory and peripherals low design efforts due to software and hardware compatibility reduced system costs due to intelligent on-chip components, e.g. power-on-clear, lowe voltage indication, internal ring oscillator, lin, advanced full can, etc. 30 chapter 1 outline (pd780816 subseries) user?s manual u15251ee4v0ud00 the major functional differences between the subseries are shown below. note: under development (target values) table 1-1: the major functional differences between the subseries function rom (bytes) timer a/d lcd serial interfaces meter c/d i/o v dd min value subseries name 8-bit 16- bit wt wdt 8-bit 10-bit special assp pd780816a, pd780816b 32 k to 60 k 2 ch 2 ch 1 ch 1 ch 12 ch -- csi: 2 ch uart: 1 ch dcan: 1 ch - 46 4.0 v pd780703ay 59.5 k 3 ch 16 ch i2c: 1 ch csi: 2 ch uart: 1 ch dcan: 1 ch 67 3.5 v pd780822b 90 k to 120 k 2 ch 4 ch - 8 ch 34 x 4 csi: 2 ch uart with lin: 1 ch dcan: 1 ch 4 instr, 2 coils 76 4.0 v pd780828a 32 k to 60 k 3 ch 1 ch 5 ch - 28 x 4 csi: 2 ch uart: 1 ch dcan: 1 ch 59 pd780948a 60 k 2 ch 2 ch 8 ch 40 x 4 - 79 f-line note 78k0/fc2 32 k to 60 k 4 ch 2 ch 1 ch 1 ch - 8 ch - uart with lin/ csi (spi comp.): 1 ch uart with lin: 1 ch afcan: 1 ch - 37/ 40 1.8 v 78k0/fe2 48 k to 128 k 2 ch 12 ch csi (spi comp.): 1 ch uart with lin/ csi (spi comp.): 1 ch uart with lin: 1 ch afcan: 1 ch 55 78k0/ff2 60 k to 128 k 4 ch 16 ch csi (spi comp.): 1 ch uart with lin/ csi (spi comp.): 1 ch uart with lin: 1 ch afcan: 1 ch 71 31 chapter 1 outline (pd780816 subseries) user?s manual u15251ee4v0ud00 1.7 block diagram figure 1-3: block diagram remark: the internal rom and ram capacity depends on the product. port 0 78k/0 cpu core port 1 port 2 port 4 port 5 port 6 port 7 main clock monitor ti00/to0 sck2 so2 si2 standby control 16 bit timer 0 ti21 16 bit timer 2 8 bit timer 50 watch timer serial interface channel (sio2) rxd txd uart0 pcl clock output control a/d converter / ani0- ani11 avss av dd /av ref dcan interface ram interface v dd1 v dd0 v ss1 v ss0 ic/v pp crxd ctxd system control 5v x1 x2 reset watchdog timer power fail detector rom / flash ram 8 mhz / rc oscillator cl1 cl2 cclk 4 8 8 8 8 2 (key interrupt port) interrupt control intp0- intp3 ti01 ti20 ti22 ti50/to50 8 bit timer 51 ti51/to51 8 sck3 so3/sio3 si3 serial interface channel (sio3) 32 chapter 1 outline (pd780816 subseries) user?s manual u15251ee4v0ud00 1.8 overview of functions table 1-2: overview of functions part number pd780814 pd780816 pd78f0818 item internal memory rom 32 kbytes mask rom 48 kbytes mask rom 59.5 kbytes flash ee internal high-speed ram 1024 bytes 1024 bytes 1024 bytes internal expansion ram 480 bytes 480 bytes 2016 bytes memory space 64 kbytes general registers 8 bits u 32 registers (8 bits u 8 registers u 4 banks) instruction cycle on-chip instruction execution time selection function when main system clock selected 0.25 s/0.5 s/1 s/2 s/4 s (at 8 mhz) when subsystem clock selected 122 s (at 32.768 khz) main system clock 0.25 s/0.5 s/1 s/2 s/4 s (at 8 mhz) instruction set 16-bit operation multiplication/division (8 bits u 8 bits, 16 bits y 8 bits) bit manipulation (set, reset, test, boolean operation) bcd adjustment, etc. i/o ports to t a l : 4 6 cmos input: 8 cmos i/o: 36 a/d converter 8 bit resolution u 12 channels serial interface 3-wire mode: 1 channel 2-wire/3-wire mode: 1 channel uart mode: 1 channel timer 16 bit timer / event counter: 2 channels 8 bit timer / event counter: 2 channels watch timer: 1 channel watchdog timer: 1 channel timer output 3 outputs (16-bit pwm u 1, 8-bit pwm output u 2) main clock monitor main clock oscillation fail detection clock output 8 mhz, 4 mhz, 2 mhz, 1 mhz, 500 khz, 250 khz, 125 khz, 62.5 khz at main system clock of 8 mhz can 1 channel vectored interrupts maskable interrupts internal: 22 external: 4 non-maskable interrupts internal: 1 software interrupts internal: 1 supply voltage v dd = 4.0 v to 5.5 v package 64-pin plastic qfp (12 u 12 mm) 33 chapter 1 outline (pd780816 subseries) user?s manual u15251ee4v0ud00 1.9 differences between flash and mask rom version the differences between the two versions are shown in the table below. differences of the electrical specification are given in the data sheet. table 1-3: differences between flash and mask rom version flash version mask rom version rom flash eeprom mask rom internal rom capacity pd78f0818: 59.5 kbytes pd780814: 32 kbytes pd780816: 48 kbytes icc pin none available v pp pin available none 34 user?s manual u15251ee4v0ud00 [memo] 35 user?s manual u15251ee4v0ud00 chapter 2 pin functi on (pd780816 subseries) 2.1 pin function list normal operating mode pins / pin input/output types table 2-1: pin input/output types input/output pin name function alternate function after reset input/output p00 port 0 4-bit input / output port input / output mode can be specified bit-wise if used as an input port, a pull-up resistor can be connected by software bit-wise intp0 input p01 intp1 input p02 intp2 input p03 intp3 input input p10-p17 port 1 8-bit input port ani0-ani7 input input/output p20 port 2 8-bit input / output port input / output mode can be specified bit-wise if used as an input port, a pull-up resistor can be specified bit-wise si2 input p21 so2 input p22 sck2 input p23 pcl input p24 rxd input p25 txd input p26 ti50/to50 input p27 ti51/to51 input input/output p40-p47 port 4 8-bit input / output port input / output mode can be specified bit-wise if used as an input port, a pull-up resistor can be connected by software kr0-kr7 input input/output p50-p57 port 5 8-bit input / output port input / output mode can be specified bit-wise if used as an input port, a pull-up resistor can be specified bit-wise - input input/output p60 port 6 8-bit input / output port input / output mode can be specified bit-wise if used as an input port, a pull-up resistor can be connected by software ti20 input p61 ti21 p62 ti22 p63 - p64 - p65 sck3 p66 so3/sio2 p67 si3 input/output p70 port 7 2-bit input / output port input / output mode can be specified bit-wise if used as an input port, a pull-up resistor can be specified bit-wise ti00/to00 input p71 ti01 36 chapter 2 pin function (pd780816 subseries) user?s manual u15251ee4v0ud00 2.2 non-port pins table 2-2: non-port pins (1/2) pin name input/output function after reset alternate function pin intp0 input external interrupts with specifiable valid edges (rising edge, falling edge, both rising and falling edges) input p00 intp1 p01 intp2 p02 intp3 p03 si2 input serial interface serial data input input p20 si3 input serial interface serial data input input p67 so2 output serial interface serial data output input p21 so3 output serial interface serial data output input p66 sck2 input/output serial interface serial clock input / output input p22 sck3 input/output serial interface serial clock input / output input p65 sio3 input/output serial interface serial data input / output input p66 rxd input asynchronous serial interface serial data input input p24 txd0 output asynchronous serial interface serial data output input p25 crxd input can serial data input input - ctxd output can serial data output output - cclk input can serial clock input - cl1 ti00 input external signal input to 16-bit timer tmo input p70/to0 ti01 ti20 capture trigger input p64 ti21 capture trigger input p65 ti22 capture trigger input p90/s23 ti50 external count clock input to 8-bit timer (tm50) p34/to50/s27 ti51 external count clock input to 8-bit timer (tm51) p91/to51/s22 to0 output 16-bit timer output input p70/ti00 to50 8-bit timer output (als o used for pwm output) p26/ti50 to51 8-bit timer output (als o used for pwm output) p27/ti51 pcl output clock output (for main system clock trimming) input p23 ani0 - ani7 input ad converter analog input input p10-p17 ani8 - ani11 input ad converter analog input input - av dd /av ref - ad converter reference voltage input. power supply of the ad converter. -- av ss - ad converter ground potential. connect to v ss -- reset input system reset input - - x1 - crystal connection for main system clock - - x2 - crystal connection for main system clock - - cl1 input rc connection for subsystem clock - cclk cl2 - rc connection for subsystem clock - - 37 chapter 2 pin function (pd780816 subseries) user?s manual u15251ee4v0ud00 v dd0 ,v dd1 - positive power supply - - v ss0 ,v ss1 - ground potential - - v pp - high voltage supply for flash programming (only flash version) -ic ic - internal connection. connect directly to v ss (only mask rom version) - v pp table 2-2: non-port pins (2/2) pin name input/output function after reset alternate function pin 38 chapter 2 pin function (pd780816 subseries) user?s manual u15251ee4v0ud00 2.3 description of pin functions 2.3.1 p00 to p03 (port 0) this is an 4-bit input/output port. besides serving as input/output port the external interrupt input is implemented. (1) port mode p00 to p03 function as input/output ports. p00 to p03 can be specified for input or output bit-wise with a port mode register. when they are used as input ports, pull-up resistors can be connected to them by defining the pull-up resistor option register 0. (2) control mode in this mode, this port functions as external interrupt input. intp0 to intp3 intp0 to intp3 are external input pins which can specify valid edges (risin g, falling or rising and falling) of this external interrupt pins. 2.3.2 p10 to p17 (port 1) these pins constitute ab 8-bit input only port. in addi tion, they are also used to input a/d converter ana- log signals. the following operating modes can be specified bit-wise. (1) port mode in this mode, p10 to p17 function as an 8-bit input only port. (2) (2) control mode in this mode, p10 to p17 function as a/d converter analog input pins (ani0 to ani7). 2.3.3 p20 to p27 (port 2) these are 8-bit input/output ports. besides serving as input/output ports, they function as data input/ output to/from and clock input/out of the serial interface csi or data transmit and receive of the uart. additionally they function as timer in put/output and processor clock output (1) port mode in this mode, p20 to p27 function as an 8-bit input/output port. p20 to p27 can be specified for input or output bit wise with a port mode register. when they are used as input ports, pull-up resis- tors can be connected to them by defining the pull-up resistor option register 2. (2) control mode these ports function as timer input/output, as serial interface data input/output, serial clock input/ output, uart transmit and receive and as processor clock output. (a) si2, so2 serial interface serial data input/output pins. (b) sck2 serial interface serial clock input/output pins. 39 chapter 2 pin function (pd780816 subseries) user?s manual u15251ee4v0ud00 (c) ti50 pin for external count clock input to 8-bit timer/event counter 50. (d) to50 pin for output of the 8-bit timer/event counter 50. (e) ti51 pin for external count clock input to 8-bit timer/event counter 51. (f) to51 pin for output of the 8-bit timer/event counter 51. (g) rxd, txd asynchronous serial interface data input/output pins. (h) pcl clock output pin. caution: when this port is used as a serial interface, the i/o function and output latches must be set according to the function the user requires. 2.3.4 p40 to p47 (port 4) this is an 8-bit input/output port. besides serving as input/output port, they function as key return sig- nal. the following operating modes can be specified bit-wise or byte-wise. (1) port mode these ports function as 8-bit input/output ports. they can be specified bit-wise as input or output ports with port mode register 4. when they are used as input ports, pull-up resistors can be con- nected to them by defining the pull-up resistor option register 4. (2) control mode these ports function as key return signal by detection of a low level at this port pins. 2.3.5 p50 to p57 (port 5) these ports function as 8-bit input/output ports. they can be specified bit-wise as input or output ports with port mode register 5. when they are used as input ports, pull-up resistors can be connected to them by defining the pull-up resistor option register 5. 40 chapter 2 pin function (pd780816 subseries) user?s manual u15251ee4v0ud00 2.3.6 p60 to p65 (port 6) these are 6-bit input/output ports. beside serving as input/output ports, they function as timer capture input. the following operating modes can be specified bit-wise. (1) port mode these ports function as 8-bit input/output ports. they can be specified bit-wise as input or output ports with port mode register 6. when they are used as input ports, pull-up resistors can be con- nected to them by defining the pull-up resistor option register 6. (2) control mode these ports function as timer capture input. (a) ti20, ti21, ti22 pins for external capture trigger input to the 16-bit timer capture registers of tm2. (b) si3, so3, sio3 serial interface serial data input/output pins. (c) sck3 serial interface serial clock input/output pin. 2.3.7 p70, p71 (port 7) these are 2-bit input/output ports. besides servin g as input/output ports, they function timer input/ output. the following operating modes can be specified bit-wise or byte-wise. (1) port mode these ports function as 2-bit input/output ports. they can be specified bit-wise as input or output ports with port mode register 7. when they are used as input ports, pull-up resistors can be con- nected to them by defining the pull-up resistor option register 7. (2) control mode in this mode, these port functions as external count clock and capture trigger signal input of the 16-bit timer and as timer signal output. (a) ti00 pin for external count clock input to the 16-bit timer/event counter and pin for capture trigger signal input to the 16-bit timer/event counter capture register. (b) ti01 pin for external count clock input to the 16-bit timer/event counter and pin for capture trigger signal input to the 16-bit timer/event counter capture register. to0 pin for output of the 16-bit timer/event counter. 41 chapter 2 pin function (pd780816 subseries) user?s manual u15251ee4v0ud00 2.3.8 ctxd this pin functions as can-controller transmit output. 2.3.9 crxd this pin functions as can- controller receive input. 2.3.10 cclk this pin functions as can-controller clock supply input. 2.3.11 ani0 to ani11 these pins constitute an analog input only port. 2.3.12 av dd /av ref a/d converter reference voltage input pin and the power supply for the a/d-converter. when a/d converter is not used, connect this pin to v dd . 2.3.13 av ss this is a ground voltage pin of a/d converter. always use the same voltage as that of the v ss pin even when a/d converter is not used. 2.3.14 reset this is a low-level active system reset input pin. 2.3.15 x1 and x2 crystal resonator connect pins for main system clock oscillati on. for external clock supply, input it to x1. 2.3.16 cl1 and cl2 rc connect pins for sub system clock oscillation. 2.3.17 v dd0 , v dd1 v dd0 is the positive power supply pin for ports. v dd1 is the positive power supply pin for blocks other than ports. 2.3.18 v ss0 , v ss1 v ss0 is the ground pin for ports. v ss1 is the ground pin for blocks other than ports. 42 chapter 2 pin function (pd780816 subseries) user?s manual u15251ee4v0ud00 2.3.19 v pp (pd78f0818 only) high-voltage apply pin for flash programming mode setting. connect this pin directly to v ss in normal operating mode. 2.3.20 ic (mask rom version only) the ic (internally connected) pin is provided to set the test mode to check the pd780814 and pd780816 at delivery. connect it directly to the v ss with the shortest poss ible wire in the normal operating mode. when a voltage difference is produced between the ic pin and v ss pin because the wiring between those two pins is too long or an external noise is input to the ic pin, the user?s program may not run normally. figure 2-1: connection of ic pins caution: connect ic pins to v ss pins directly. vic as short as possible ss 43 chapter 2 pin function (pd780816 subseries) user?s manual u15251ee4v0ud00 2.4 pin i/o circuits and recommended connection of unused pins the input/output circuit type of each pin and recommended connection of unused pins are shown in the following table. for the input/output circuit configuration of each ty pe, see ttable 2-3, ?types of pin input/output cir- cuits,? on page 43. table 2-3: types of pin input/output circuits (1/2) pin name input/output circuit type i/o recommended connection for unused pins p00/intp0 8-a i/o input: connect to v dd or v ss via a resistor individually. output: leave open. p01/intp1 p02/intp2 p03/intp3 p10/ani0 11-b i connect directly to v dd or v ss p11/ani1 p12/ani2 p13/ani3 p14/ani4 p15/ani5 p16/ani6 p17/ani7 ani8 note ani9 note ani10 note ani11 note p20/si2 10-a i/o input: connect to v dd or v ss via a resistor individually. output: leave open. p21/so2 p22/sck2 p23/pcl 5-a p24/rxd 8-a p25/txd 5-a p26/ti50/to50 8-a p27/ti51/to51 8-a p40/kr0 5-a i/o input: connect to v dd or v ss via a resistor individually. output: leave open. p41/kr1 p42/kr2 p43/kr3 p44/kr4 p45/kr5 p46/kr6 p47/kr7 note: ani8 to ani11 have the same input/output circuit li ke p10/ani0 to p17/ani7, but the input port function of ani8 to ani11 is not implemented. 44 chapter 2 pin function (pd780816 subseries) user?s manual u15251ee4v0ud00 p50 5-a i/o input: connect to v dd or v ss via a resistor individually. output: leave open. p51 p52 p53 p54 p55 p56 p57 p60/ti20 8-a i/o input: connect to v dd or v ss via a resistor individually. output: leave open. p61ti21 p62/ti22 p63 p64 p65/sck3 p66/so3/sio3 p67/si3 p70/ti00/to00 8-a i/o input: connect to v dd or v ss via a resistor individually. output: leave open. p71/ti01 crxd 1 i connect to v dd or v ss via a resistor individually ctxd 2 o leave open cl1/cclk - i gnd cl2 - - leave open reset 1-- av dd / av ref -- connect to v dd av ss -- connect to v ss ic -- connect directly to v ss v pp table 2-3: types of pin input/output circuits (2/2) pin name input/output circuit type i/o recommended connection for unused pins 45 chapter 2 pin function (pd780816 subseries) user?s manual u15251ee4v0ud00 figure 2-2: pin input/output circuits type 1 in type 2 pullup enable data output disable v p-ch n-ch p-ch in/out dd v dd type 5-a input enable data v p-ch n-ch out dd type 10-a pullup enable data open drain output disable v p-ch n-ch p-ch in/out dd v dd type 11-b p-ch n-ch input enable + - v ref (threshold voltage) in comparator type 8-a pullup enable data output disable v p-ch n-ch p-ch in/out dd v dd 46 user?s manual u15251ee4v0ud00 [memo] 47 user?s manual u15251ee4v0ud00 chapter 3 cpu architecture 3.1 memory space the memory map of the pd780814 is shown in figure 3-1. figure 3-1: memory map 0f the pd780814 note: in the expansion ram between f600h and f7dfh it is not possible to do code execution. ffffh ff00h feffh fee0h fedfh 0000h 7fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h expansion ram 480 x 8 bits program area callf entry area program area callt table area vector table area special function register (sfr) 256 x 8 bits general registers 32 x 8 bits internal high-speed ram 1024 x 8 bits internal mask rom 32768 x 8 bits not usable not usable ff20h ff1fh fe20h faffh f7e0h f7dfh f600h f5ffh 8000h 7fffh fb00h (shared with dcan) 48 chapter 3 cpu architecture user?s manual u15251ee4v0ud00 the memory map of the pd780816 is shown in figure 3-2. figure 3-2: memory map of the pd780816 note: in the expansion ram between f600h and f7dfh it is not possible to do code execution. ffffh ff00h feffh fee0h fedfh 0000h bfffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h expansion ram 480 x 8 bits program area callf entry area program area callt table area vector table area special function register (sfr) 256 x 8 bits general registers 32 x 8 bits internal high-speed ram 1024 x 8 bits internal mask rom 49152 x 8 bits not usable not usable ff20h ff1fh fe20h faffh f7e0h f7dfh f600h f5ffh c000h bfffh fb00h (shared with dcan) 49 chapter 3 cpu architecture user?s manual u15251ee4v0ud00 the memory map of the pd78f0818 is shown in figure 3-3. figure 3-3: memory map of the pd78f0818 notes: 1. in the expansion ram between f000h and f5ffh it is possible to do code execution. 2. in the expansion ram between f600h and f7dfh it is not possible to do code execution. ffffh ff00h feffh fee0h fedfh 0000h edffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h expansion ram 480 x 8 bits program area callf entry area program area callt table area vector table area special function register (sfr) 256 x 8 bits general registers 32 x 8 bits internal high-speed ram 1024 x 8 bits internal mask rom 60928 x 8 bits not usable not usable ff20h ff1fh fe20h faffh f7e0h f7dfh f600h f5ffh ee00h edffh fb00h (shared with dcan) expansion ram 1536 x 8 bits f000h efffh 50 chapter 3 cpu architecture user?s manual u15251ee4v0ud00 3.1.1 internal program memory space the internal program memory space stores programs and table data. this is generally accessed by the program counter (pc). the pd780816 subseries has various size of internal roms or flash eprom as shown below. the internal program memory is divided into three areas: vector table area, callt instruction table area, and callf instruction table area. these areas are described on the next page. table 3-1: internal rom capacities part number internal rom type capacity pd780814 mask rom 32768 u 8-bits pd780816 mask rom 49152 u 8-bits pd78f0818 flash eeprom 60928 u 8-bits 51 chapter 3 cpu architecture user?s manual u15251ee4v0ud00 (1) vector table area the 64-byte area 0000h to 003fh is reserved as a vector table area. the reset input and program start addresses for branch upon generation of each interrupt request are stored in the vector table area. of the 16-bit address, low-order 8 bits are stor ed at even addresses and high-order 8 bits are stored at odd addresses. table 3-2: vectored interrupts vector table address interrupt request 0004h inwdt 0006h intad 0008h intovf 000ah inttm20 000ch inttm21 000eh inttm22 0010h intp0 0012h intp1 0014h intp2 0016h intp3 0018h intce 001ah intcr 001ch intct0 001eh intct1 0020h intcsi20 0022h intser 0024h intsr 0026h intst 0028h inttm00 002ah inttm01 002ch inttm50 002eh inttm51 0032h intwti 0034h intwt 0036h intkr 0038h intcsi30 003eh brk 52 chapter 3 cpu architecture user?s manual u15251ee4v0ud00 (2) callt instruction table area the 64-byte area 0040h to 007fh can store the subroutine entry address of an 1-byte call instruc- tion (callt). (3) callf instruction entry area the area 0800h to 0fffh can perform a direct subroutine call with a 2-byte call instruction (callf). 53 chapter 3 cpu architecture user?s manual u15251ee4v0ud00 3.1.2 internal data memory space the pd780816 subseries units incorporate the following rams. (1) internal high-speed ram the 32-byte area fee0h to feff is allocated with four general purpose register banks composed of eight 8-bit registers. the internal high-speed ram has to be used as a stack memory. (2) internal expansion ram 3.1.3 special function register (sfr) area an on-chip peripheral hardware special function register (sfr) is allocated in the area ff00h to ffffh. (refer to table 3-5, ?special function register list,? on page 62 ). caution: do not access addresses where the sfr is not assigned. table 3-3: internal high-speed ram device internal high speed ram pd780814 1024 u 8 bits (fb00h to feffh) pd780816 1024 u 8 bits (fb00h to feffh) pd78f0818 1024 u 8 bits (fb00h to feffh) table 3-4: internal expansion ram (including sharing with dcan) device internal expansion ram pd780814 480 u 8 bits (f600h to f7dfh) pd780816 480 u 8 bits (f600h to f7dfh) pd78f0818 2016 u 8 bits (f000h to f7dfh) 54 chapter 3 cpu architecture user?s manual u15251ee4v0ud00 3.1.4 data memory addressing the pd780816 subseries is provided with a verity of addressing modes which take account of mem- ory manipulability, etc. special add ressing methods are possible to me et the functions of the special function registers (sfrs) and general registers. the data memory space is the entire 64k-byte space (0000h to ffffh). figures 3-4 to 3-6 show the data memory addressing modes. for details of addressing, refer to 3.4 ?operand address addressing? on page 69 . figure 3-4: data memory addressing of pd780814 note: in the expansion ram between f600h and f7dfh it is not possible to do code execution. ffffh ff00h feffh fee0h fedfh 8000h 7fffh 0000h expansion ram 480 x 8 bits (shared with dcan) special function register (sfr) 256 x 8 bits general registers 32 x 8 bits internal high-speed ram 1024 x 8 bits internal mask rom 32768 x 8 bits not usable not usable ff20h ff1fh fe20h fb00h faffh f7e0h f7dfh f600h f5ffh sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing 55 chapter 3 cpu architecture user?s manual u15251ee4v0ud00 figure 3-5: data memory addressing of pd780816 note: in the expansion ram between f600h and f7dfh it is not possible to do code execution. ffffh ff00h feffh fee0h fedfh c000h bfffh 0000h expansion ram 480 x 8 bits (shared with dcan) special function register (sfr) 256 x 8 bits general registers 32 x 8 bits internal high-speed ram 1024 x 8 bits internal mask rom 49152 x 8 bits not usable not usable ff20h ff1fh fe20h fb00h faffh f7e0h f7dfh f600h f5ffh sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing 56 chapter 3 cpu architecture user?s manual u15251ee4v0ud00 figure 3-6: data memory addressing of pd78f0818 notes: 1. in the expansion ram between f000h and f5ffh it is possible to do code execution. 2. in the expansion ram between f600h and f7dfh it is not possible to do code execution. ffffh ff00h feffh fee0h fedfh ee00h edffh 0000h expansion ram 1536 x 8 bits special function register (sfr) 256 x 8 bits general registers 32 x 8 bits internal high-speed ram 1024 x 8 bits internal mask rom 60928 x 8 bits not usable not usable ff20h ff1fh fe20h fb00h faffh f7e0h f7dfh f000h efffh sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing f600h f5ffh expansion ram 480 x 8 bits (shared with dcan) 57 chapter 3 cpu architecture user?s manual u15251ee4v0ud00 3.2 processor registers the pd780816 subseries units incorporate the following processor registers. 3.2.1 control registers the control registers control the program sequence, statuses, and stack memory. the control registers consist of a program counter, a program status word and a stack pointer. (1) program counter (pc) the program counter is a 16-bit register which holds the address information of the next program to be executed. in normal operation, the pc is automatically incremented according to the number of bytes of the instruction to be fetched. when a branch instruction is executed, immediate data and register con- tents are set. reset input sets the reset vector table values at addresses 0000h and 0001h to the program counter. figure 3-7: program counter configuration (2) program status word (psw) the program status word is an 8-bit register consisting of various flags to be set/reset by instruc- tion execution. program status word contents are automatically stacked upon interrupt request generation or push psw instruction execution and are automatically reset upon execution of the retb, reti and pop psw instructions. reset input sets the psw to 02h. figure 3-8: program status word configuration pc 15 0 ie 7 0 z rbs1 rbs0 ac 0 isp cy 58 chapter 3 cpu architecture user?s manual u15251ee4v0ud00 (a) interrupt enable flag (ie) this flag controls the interrupt request acknowledge operations of the cpu. when 0, the ie is set to interrupt disabled (di) status. all interrupts except non-maskable interrupt are disabled. when 1, the ie is set to interrupt enabled (ei) status and interrupt request acknowledge is control- led with an in-service priority flag (isp), an interrupt mask flag for various interrupt sources, and a priority specification flag. the ie is reset to (0) upon di instruction execution or interrupt request acknowledgement and is set to (1) upon ei instruction execution. (b) zero flag (z) when the operation result is zero, this flag is set (1). it is reset (0) in all other cases. (c) register bank select flags (rbs0 and rbs1) these are 2-bit flags to select one of the four register banks. in these flags, the 2-bit information which indicates the register bank selected by sel rbn instruc- tion execution is stored. (d) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). it is reset (0) in all other cases. (e) in-service priority flag (isp) this flag manages the priority of acknowledge able maskable vectored interrupts. when 0, acknowledgment of the vectored interrupt request specified to low-order priority with the priority specify flag registers (pr0l, pr0h, pr1l and pr1h) is disabled. whether an actual interrupt request is acknowledged or not is controlled with the interrupt enable flag (ie). (f) carry flag (cy) this flag stores overflow and underflow upon add/s ubtract instruction execution. it stores the shift- out value upon rotate instruction execution and functions as a bit accumulator during bit manipula- tion instruction execution. 59 chapter 3 cpu architecture user?s manual u15251ee4v0ud00 (3) stack pointer (sp) this is a 16-bit register to hold the start address of the memory stack area. only the internal high- speed ram area can be set as the stack area. figure 3-9: stack pointer configuration the sp is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory. each stack operation saves/resets data as shown in figures 3-10 and 3-11. caution: since reset input makes sp contents indeterminate, be sure to initialize the sp before instruction execution. figure 3-10: data to be saved to stack memory figure 3-11: data to be reset to stack memory sp 15 0 interrupt and brk instruction psw pc15 to pc8 pc15 to pc8 pc7 to pc0 register pair lower sp sp _ 2 sp _ 2 register pair upper call, callf, and callt instruction push rp instruction sp _ 1 sp sp sp _ 2 sp _ 2 sp _ 1 sp pc7 to pc0 sp _ 3 sp _ 2 sp _ 1 sp sp sp _ 3 reti and retb instruction psw pc15 to pc8 pc15 to pc8 pc7 to pc0 register pair lower sp sp + 2 sp register pair upper ret instruction pop rp instruction sp + 1 pc7 to pc0 sp sp + 2 sp sp + 1 sp + 2 sp sp + 1 sp sp + 3 60 chapter 3 cpu architecture user?s manual u15251ee4v0ud00 3.2.2 general registers a general register is mapped at particular addresses (fee0h to feffh) of the data memory. it consists of 4 banks, each bank consisting of eight 8-bit registers (x, a, c, b, e, d, l, and h). each register can also be used as an 8-bit register . two 8-bit registers can be used in pairs as a 16-bit register (ax, bc, de, and hl). they can be described in terms of function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) and absolute names (r0 to r7 and rp0 to rp3). register banks to be used for instruction execution are set with the cpu control instruction (sel rbn). because of the 4-register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interruption for each bank. figure 3-12: general register configuration (a) absolute name (b) function name bank0 bank1 bank2 bank3 feffh fef8h fee0h rp3 rp2 rp1 rp0 r7 15 0 7 0 r6 r5 r4 r3 r2 r1 r0 16-bit processing 8-bit processing fee0h fee8h bank0 bank1 bank2 bank3 feffh fef8h fee0h hl de bc ax h 15 0 7 0 l d e b c a x 16-bit processing 8-bit processing fef0h fee8h 61 chapter 3 cpu architecture user?s manual u15251ee4v0ud00 3.2.3 special function register (sfr) unlike a general register, each special function register has special functions. it is allocated in the ff00h to ffffh area. the special function registers can be manipulated in a similar way as the general registers, by using operation, transfer, or bit-manipulate instructions. the special function registers are read from and writ- ten to in specified manipulation bit units (1, 8, and/or 16) depending on the register type. each manipulation bit unit can be specified as follows. 1-bit manipulation describe the symbol reserved with assembler for the 1-bit manipulation instruction operand (sfr.bit). this manipulation can also be specified with an address. 8-bit manipulation describe the symbol reserved with assembler for the 8-bit manipulation instruction operand (sfr). this manipulation can also be specified with an address. 16-bit manipulation describe the symbol reserved with assembler for the 16-bit manipulation instruction operand (sfrp). when addressing an address, describe an even address. table 3-5, ?special function register list,? on pa ge 62 gives a list of special function registers. the meaning of items in the table is as follows. symbol the assembler software ra78k0 translates th ese symbols into corresponding addresses where the special function registers are allocated. these symbols should be used as instruction operands in the case of programming. r/w this column shows whether the corresponding special function register can be read or written. r/w : both reading and writing are enabled. r : the value in the register can read out. a write to this register is ignored. w : a value can be written to the register. reading values from the register is impossible. manipulation the register can be manipulated in bit units. after reset the register is set to the value immediately after the reset signal is input. 62 chapter 3 cpu architecture user?s manual u15251ee4v0ud00 table 3-5: special function register list (1/3) address sfr name symbol r/w manipulation bit unit after reset 1-bit 8-bit 16-bit ff00h port 0 p0 r/w u u - 00h ff01h port 1 p1 r u u - 00h ff02h port 2 p2 r/w u u - 00h ff04h port 4 p4 r/w u u - 00h ff05h port 5 p5 r/w u u - 00h ff06h port 6 p6 r/w u u - 00h ff07h port 7 p7 r/w u u - 00h ff10h 16-bit timer/counter register 0 tm0 tm0l r- - u 00h ff11h tm0h ff12h 8-bit timer register 50 tm50 r - u - 00h ff13h 8-bit timer register 51 tm51 r - u - 00h ff14h 16-bit capture/compare register 00 cr00 cr00l r/w - - u 00h ff15h cr00h ff16h 16-bit capture/compare register 01 cr01 cr01l r/w - - u 00h ff17h cr01h ff18h compare register 50 cr50 r/w - u - 00h ff19h compare register 51 cr51 r/w - u - 00h ff1bh a/d conversion result register adcr1 r - u - 00h ff1fh serial i/o shift register 20 sio20 r/w - u - 00h ff20h port mode register 0 pm0 r/w u u -ffh ff22h port mode register 2 pm2 r/w u u -ffh ff24h port mode register 4 pm4 r/w u u -ffh ff25h port mode register 5 pm5 r/w u u -ffh ff26h port mode register 6 pm6 r/w u u -ffh ff27h port mode register 7 pm7 r/w u u -ffh ff30h pull-up resistor opt ion register 0 pu0 r/w u u - 00h ff32h pull-up resistor opt ion register 2 pu2 r/w u u - 00h ff34h pull-up resistor opt ion register 4 pu4 r/w u u - 00h ff35h pull-up resistor opt ion register 5 pu5 r/w u u - 00h ff36h pull-up resistor opt ion register 6 pu6 r/w u u - 00h ff37h pull-up resistor opt ion register 7 pu7 r/w u u - 00h ff40h clock output select register cks r/w u u - 00h ff41h watch timer mode register wtm r/w u u - 00h ff42h watchdog timer clock selection register wdcs r/w u u - 00h ff47h key return mode register krm r/w u u - 00h ff48h ext. int rising edge enable register egp r/w u u - 00h ff49h ext. int falling edge enable register egn r/w u u - 00h ff50h flash programming mode control register flpmc r/w u u - 08h ff51h self-programming and oscillation control register spoc r/w u u - 08h ff52h port function register 2 pf2 r/w u u - 00h ff60h 16-bit timer mode control register 0 tmc0 r/w u u - 00h 63 chapter 3 cpu architecture user?s manual u15251ee4v0ud00 ff61h prescaler mode register 0 prm0 r/w - u -00h ff62h capture/compare control register 0 crc0 r/w - u -00h ff63h 16-bit timer output control register 0 toc0 r/w u u -00h ff65h 16-bit timer mode control register 2 tmc2 r/w u u -00h ff66h prescaler mode register 2 prm2 r/w - u -00h ff67h capture/compare control register 2 crc2 r/w - u -00h ff68h 16-bit timer/counter register 2 tm2 tm2l r- - u 0000h ff69h tm2h ff6ah 16-bit capture register 20 cr20 cr20l r- - u 0000h ff6bh cr20h ff6ch 16-bit capture register 21 cr21 cr21l r- - u 0000h ff6dh cr21h ff6eh 16-bit capture register 22 cr22 cr22l r- - u 0000h ff6fh cr22h ff70h 8-bit timer mode control register 50 tmc50 r/w u u -00h ff71h timer clock selection register 50 tcl50 r/w - u -00h ff74h 8-bit timer mode control register 51 tmc51 r/w u u -00h ff75h timer clock selection register 51 tcl51 r/w - u -00h ff77h clock monitor mode register clm r/w u u -00h ff98h a/d converter mode register 1 adm1 r/w u u -00h ff99h analog channel select register 1 ads1 r/w - u -00h ff9ah power fail comparator mode register pfm r/w u u -00h ff9bh power fail comparator threshold register pft r/w - u -00h ff9ch d/a converter channel 0 mode register note dam0 r/w u u -00h ffa0h uart operation mode register asim0 r/w u u -00h ffa1h uart receive status register asis0 r - u -00h ffa2h baud rate generator control register brgc0 r/w - u -00h ffa3h transmit shift register txs0 w - u -ffh receive buffer register rxb0 r - u -ffh ffa8h serial mode register 20 csim20 r/w u u -00h ffa9h serial receive data buffer sirb20 r - u -00h ffaah receive data buffer status srbs20 r - u -00h ffadh serial i/o shift register 30 sio30 r/w - u -00h ffaeh serial i/o switch register sioswi r/w u u -00h ffafh serial i/o mode register 30 csim30 r/w u u -00h ffb0h can control register canc r/w u u -01h ffb1h transmit control register tcr r/w - u -00h ffb2h received message register rmes r - u -00h ffb3h redefinition cont rol register redef r/w u u -00h ffb4h can error status register canes r/w - u -00h ffb5h transmit error counter tec r - u -00h note: this register is needed for the emulation of power fa il detect (pfd) function. dam0 is not available in this product. table 3-5: special function register list (2/3) address sfr name symbol r/w manipulation bit unit after reset 1-bit 8-bit 16-bit 64 chapter 3 cpu architecture user?s manual u15251ee4v0ud00 ffb6h receive error counter rec r - u - 00h ffb7h message count register mcnt r/w - u - 00h ffb8h bit rate prescaler brprs r/w - u -3fh ffb9h synchronous control register 0 sync0 r/w - u - 18h ffbah synchronous control register 1 sync1 r/w - u -0eh ffbbh mask control register maskc r/w - u - 00h ffe0h interrupt request flag register 0l if0 if0l r/w u u u 00h ffe1h interrupt request fl ag register 0h if0h r/w u u 00h ffe2h interrupt request flag register 1l if1 if1l r/w u u u 00h ffe3h interrupt request fl ag register 1h if1h r/w u u u 00h ffe4h interrupt mask flag register 0l mk0 mk0l r/w u u u ffh ffe5h interrupt mask fl ag register 0h mk0h r/w u u ffh ffe6h interrupt mask flag register 1l mk1 mk1l r/w u u u ffh ffe7h interrupt mask fl ag register 1h mk1h r/w u u ffh ffe8h priority order specified flag 0l pr0 pr0l r/w u u u ffh ffe9h priority order specified flag 0h pr0h r/w u u ffh ffeah priority order specified flag 1l pr1 pr1l r/w u u u ffh ffebh priority order specified flag 1h pr1h r/w u u ffh fff0h memory size switching register ims r/w - u -cfh fff4h internal expansion ram size switching register ixs r/w - u - note fff9h watchdog timer mode register wdtm r/w u u - 00h fffah oscillation stabilisation time register osts r/w - u - 04h fffbh processor clock control register pcc r/w u u - 04h note: the values after reset depend on the product (see table 22-4, ?values when the internal expansion ram size switching register is reset,? on page 387). table 3-5: special function register list (3/3) address sfr name symbol r/w manipulation bit unit after reset 1-bit 8-bit 16-bit 65 chapter 3 cpu architecture user?s manual u15251ee4v0ud00 3.3 instruction address addressing an instruction address is determined by program counter (pc) contents. the pc contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. however, when a branch instruction is executed, the branch destination information is set to the pc and branched by the following addressing. (for details of instructions, refer to 78k/0 user's manual - instructions (u12326e) . 3.3.1 relative addressing the value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (pc) and branched. the displacement value is treated as signed two?s complement data (-128 to +127) and bit 7 becomes a sign bit. in other words, the range of branch in relative addressing is between -128 and +127 of the start address of the following instruction. this function is carried out when the br $addr16 instruction or a conditional branch instruction is executed. figure 3-13: relative addressing 15 0 pc + 15 0 876 s 15 0 pc a jdisp8 when s = 0, all bits of a are 0. when s = 1, all bits of a are 1. pc indicates the start address of the instruction after the br instruction. ... 66 chapter 3 cpu architecture user?s manual u15251ee4v0ud00 3.3.2 immediate addressing immediate data in the instruction word is transferred to the program counter (pc) and branched. this function is carried out when the call!addr16 or br!addr16 or callf!addr11 instruction is exe- cuted. call!addr16 and br!addr16 instructions can branch to all the memory space. callf!addr11 instruction branches to the area from 0800h to 0fffh. figure 3-14: immediate addressing (a) in the case of call!addr16 and br!addr16 instructions (b) in the case of callf!addr11 instruction 15 0 pc 87 70 call or br low addr. high addr. 15 0 pc 87 70 fa 10?8 11 10 00001 643 callf fa 7?0 67 chapter 3 cpu architecture user?s manual u15251ee4v0ud00 3.3.3 table indirect addressing table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (pc) and branched. table indirect addressing is carried out when the callt [addr5] instruction is executed. this instruction can refer to the address stored in the memory table 40h to 7fh and branch to all the memory space. figure 3-15: table indirect addressing 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address+1 effective address 01 00000000 87 87 65 0 0 1 11 765 10 ta 4?0 operation code 68 chapter 3 cpu architecture user?s manual u15251ee4v0ud00 3.3.4 register addressing register pair (ax) contents to be specified with an instruction word are transferred to the program coun- ter (pc) and branched. this function is carried out when the br ax instruction is executed. figure 3-16: register addressing rp 15 0 pc 87 7 7 00 a x 69 chapter 3 cpu architecture user?s manual u15251ee4v0ud00 3.4 operand address addressing the following methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 implied addressing the register which functions as an accumulator (a and ax) in the general register is automatically (implicitly) addressed. of the pd780816 subseries instruction words, the following instructions employ implied addressing. operand format because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. description example in the case of mulu x with an 8-bit x 8-bit multiply instruction, the product of a register and x register is stored in ax. in this example, the a and ax registers are specified by implied addressing. table 3-6: implied addressing instruction register to be specified by implied addressing mulu a register for multiplicant and ax register for product storage divuw ax register for dividend and quotient storage adjba/adjbs a register for storage of numeric values which become decimal correction targets ror4/rol4 a register for storage of digit data which undergoes digit rotation 70 chapter 3 cpu architecture user?s manual u15251ee4v0ud00 3.4.2 register addressing the general register is accessed as an operand. the general register to be accessed is specified with register bank select flags (rbs0 and rbs1) and register specify code (rn, rpn) in the instruction code. register addressing is carried out when an instruction with the following operand format is executed. when an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. operand format ?r? and ?rp? can be described with function names (x, a, c, b, e, d, l, h, ax, bc, de and hl) as well as absolute names (r0 to r7 and rp0 to rp3). description example figure 3-17: register addressing (a) mov a, c; when selecting c register as r (b) incw de; when selecting de register pair as rp table 3-7: register addressing identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl 01100010 register specify code operation code 10000100 register specify code operation code 71 chapter 3 cpu architecture user?s manual u15251ee4v0ud00 3.4.3 direct addressing the memory indicated by immediate data in an instruction word is directly addressed. operand format description example mov a, !0fe00h; when setting !addr16 to fe00h figure 3-18: direct addressing table 3-8: direct addressing identifier description addr16 label or 16-bit immediate data operation code 10001110 op code 00000000 00h 11111110 feh 72 chapter 3 cpu architecture user?s manual u15251ee4v0ud00 3.4.4 short direct addressing the memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. the fixed space to which this addressing is applied to is the 256-byte space, from fe20h to ff1fh. an internal high-speed ram and a special function register (sfr) are mapped at fe20h to feffh and ff00h to ff1fh, respectively. the sfr area where short direct addressing is applied (ff00h to ff1fh) is a part of the sfr area. in this area, ports which are frequently accessed in a program, a compare register of the timer/event counter, and a capture register of the timer/event counter are mapped and these sfrs can be manipu- lated with a small number of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an effective address is set to 0. when it is at 00h to 1fh, bit 8 is set to 1. refer to figure 3-19 below. operand format figure 3-19: short direct addressing (a) description example mov 0fe30h, #50h; when setting saddr to fe30h and immediate data to 50h. (b) illustration table 3-9: short direct addressing identifier description saddr label of fe20h to ff1fh immediate data saddrp label of fe20h to ff1fh im mediate data (even address only) operation code 00010001 op code 00110000 30h (saddr-offset) 01010000 50h (immediate data) when 8-bit immediate data is 20h to ffh, = 0 when 8-bit immediate data is 00h to 1fh, = 1 15 0 short direct memory effective address 1 111111 87 0 7 op code saddr-offset 73 chapter 3 cpu architecture user?s manual u15251ee4v0ud00 3.4.5 special function register (sfr) addressing the memory-mapped special function register (sfr ) is addressed with 8-bit immediate data in an instruction word. this addressing is applied to the 240-byte sp aces ff00h to ffcfh and ffe0h to ffffh. however, the sfr mapped at ff00h to ff1fh can be accessed with short direct addressing. operand format figure 3-20: special-function register (sfr) addressing (a) description example mov pm0, a; when selecting pm0 (fe20h) as sfr (b) illustration table 3-10: special-function register (sfr) addressing identifier description sfr special-function register name sfrp 16-bit manipulatable special-functi on register name (even address only) operation code 11110110 op code 00100000 20h (sfr-offset) 15 0 sfr effective address 1 111111 87 0 7 op code sfr-offset 1 74 chapter 3 cpu architecture user?s manual u15251ee4v0ud00 3.4.6 register indirect addressing the memory is addressed with the contents of the register pair specified as an operand. the register pair to be accessed is specified with the register bank select flag (rbs0 and rbs1) and the register pair specify code in the instruction code. this addressing can be carried out for all the memory spaces. operand format figure 3-21: register indirect addressing (a) description example mov a, [de]; when selecting [de] as register pair (b) illustration table 3-11: register indirect addressing identifier description - [de], [hl] operation code 10000101 16 0 8 d 7 e memory the contents of addressed memory are transferred memory address specified by register pair de 7 a de 0 0 7 75 chapter 3 cpu architecture user?s manual u15251ee4v0ud00 3.4.7 based addressing 8-bit immediate data is added to the contents of the base register, that is, the hl register pair, and the sum is used to address the memory. the hl register pair to be accessed is in the register bank speci- fied with the register bank select flags (rbs0 and rbs1). addition is performed by expanding the offset data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. operand format figure 3-22: based addressing description example mov a, [hl + 10h]; when setting byte to 10h table 3-12: based addressing identifier description [hl + byte] operation code 10101110 00010000 76 chapter 3 cpu architecture user?s manual u15251ee4v0ud00 3.4.8 based indexed addressing the b or c register contents specified in an instruction are added to the contents of the base register, that is, the hl register pair, and the sum is used to address the memory. the hl, b, and c registers to be accessed are registers in the register bank specified with the register bank select flag (rbs0 and rbs1). addition is performed by expanding the contents of the b or c register as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. operand format figure 3-23: based indexed a ddressing description example in the case of mov a, [hl + b] 3.4.9 stack addressing the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatically employ ed when the push, pop, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. stack addressing enables to address the internal high-speed ram area only. figure 3-24: stack addressing description example in the case of push de table 3-13: based indexed addressing identifier description [hl + b], [hl + c] operation code 10101011 operation code 10110101 77 user?s manual u15251ee4v0ud00 chapter 4 port functions 4.1 port functions the pd780816 subseries units incorporate five input ports and thirty-eight input/output ports. figure 4-1 shows the port configuration. every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations. be sides port functions, the ports can also serve as on-chip hardware input/output pins. figure 4-1: port types port 0 p00 p60 p67 p10 p03 p17 p20 p27 p70 p71 port 6 p50 p57 port 4 p40 p47 port 7 port 1 port 5 port 2 78 chapter 4 port functions user?s manual u15251ee4v0ud00 table 4-1: pin input/output types input/ output pin name function alternate function after reset input/ output p00 port 0 4-bit input/output port input/output mode can be specified bit-wise if used an input port, a pull-up resistor can be connected by software bit-wise intp0 input p01 intp1 input p02 intp2 input p03 intp3 input input p10-p17 port 1 8-bit input only port ani0-ani7 input output p20 port 2 8-bit output only port input/output mode can be specified bit-wise if used an input port, a pull-up resistor can be connected by software bit-wise si2 input p21 so2 input p22 sck2 input p23 pc2 input p24 rxd input p25 txd input p26 ti50/to50 input p27 ti51/to51 input input/ output p40-p47 port 4 8-bit input/output port input/output mode can be specified bit-wise if used an input port, a pull-up resistor can be connected by software bit-wise kr0-kr7 input input/ output p50-p57 port 5 8-bit input/output port input/output mode can be specified bit-wise if used an input port, a pull-up resistor can be connected by software bit-wise - input input/ output p60 port 6 8-bit input/output port input/output mode can be specified bit-wise if used an input port, a pull-up resistor can be connected by software bit-wise ti20 input p61 ti21 p62 ti21 p63 - p64 - p65 sck3 p66 so3/sio3 p67 si3 input/ output p70 port 7 2-bit input/output port input/output mode can be specified bit-wise if used an input port, a pull-up resistor can be connected by software bit-wise ti00/to00 input p71 ti01 79 chapter 4 port functions user?s manual u15251ee4v0ud00 4.2 port configuration a port consists of the following hardware: note: key return mode of port 4 table 4-2: port configuration item configuration control register port mode register (pmm: m = 0, 2, 4 to 7) pull-up resistor option register (pum: m = 0, 2, 4 to 7) port function register (pfm: m = 2) key return mode register (krm) note port total: 46 ports pull-up resistor mask rom versions total: 38 pins (software-specifiable for 38 pins) pd78f0818 total: 38 pins (software-specifiable for 38 pins) 80 chapter 4 port functions user?s manual u15251ee4v0ud00 4.2.1 port 0 port 0 is an 4-bit input/output port with output latch. p00 to p03 pins can specify the input mode/output mode in 1-bit units with the port mode register 0 (pm0). when p00 to p03 pins are used as input pins, a pull-up resistor can be connected to them bit-wise with the pull-up resistor option register (pu0). dual-functions include external interrupt request input. reset input sets port 0 to input mode. figure 4-2 shows block diagram of port 0. caution: because port 0 also serves for external interrupt request input, when the port func- tion output mode is specified and the output level is changed, the interrupt request flag is set. thus, when the output mode is used, set the interrupt mask flag to 1. figure 4-2: p00 to p03 configurations remarks: 1. pu0 : pull-up resistor option register 2. pm : port mode register 3. rd : port 0 read signal 4. wr : port 0 write signal p-ch wr pm wr port rd wr pu0 v dd p00/intp0, p01/intp1, p02/intp2, p03/intp3 selector pu0 output latch (p00 to p03) pm00 to pm03 internal bus 81 chapter 4 port functions user?s manual u15251ee4v0ud00 4.2.2 port 1 port 1 is an 8-bit input only port. dual-functions include an a/d converter analog input. figure 4-3 shows a block diagram of port 1. figure 4-3: p10 to p17 configurations remark: rd: port 1 read signal rd p10/ani0 to p14/ani7 internal bus 82 chapter 4 port functions user?s manual u15251ee4v0ud00 4.2.3 port 2 port 2 is an 8-bit output port with output latch. p20 to p27 pins can specify the input mode/output mode in 1-bit units with the port mode register 2 (pm2). dual-functions include serial interface data input/output, clock input/output. when p20 to p27 pins are used as output ports, the output buffer is selectable between cmos-type or n-channel open drain. reset input sets port 2 to input mode. figure 4-4 shows a block diagram of port 2. caution: when used as a serial interface, set the input/output and input/output latch according to its functions. for the setting method, refer to the serial operating mode register format. figure 4-4: p20 to p27 configurations remarks: 1. pm : port mode register 2. rd : port 2 read signal 3. wr : port 2 write signal wr pm wr port rd selector output latch (p20 to p27) pm20 to pm27 internal bus dual function p20/si2, p21/so2, p22/sck2, p23/pcl, p24/rxd, p25/txd, p26/ti50/to50, p27/ti51/to51 83 chapter 4 port functions user?s manual u15251ee4v0ud00 4.2.4 port 4 port 4 an 8-bit input/output port with output latch. p40 to p47 pins can specify the input mode/output mode in 8-bit units with the memory expansion mode register (mm). when p40 to p47 pins are used as input pins, an on-chip pull-up resistor can be connected to them bit-wise with the pull-up resistor option register (pu4). dual-function includes the key return function. reset input sets the input mode. the port 4 block diagram is shown in figure 4-5. figure 4-5: p40 to p47 configurations remark: puo : pull-up resistor option register pm : port mode register rd : port 4 read signal wr : port 4 write signal figure 4-6: block diagram of falling edge detection circuit remark: when key return mode is enabled, a low level at any bit of port 4 generates a key return interrupt. port pins that should not generate a key return interrupt can be disabled by switching the port pin to output. p-ch wr pm wr port rd wr puo v dd p40/kr0 to p47/kr7 selector pu40 to po47 output latch (p40 to p47) pm40 to pm47 internal bus kr set signal falling edge detection circuit kr0/p40 kr1/p41 kr2/p42 kr3/p43 kr4/p44 kr5/p45 kr6/p46 kr7/p47 84 chapter 4 port functions user?s manual u15251ee4v0ud00 4.2.5 port 5 port 5 is an 8-bit output port with output latch. p50 to p57 pins can specify the input mode/output mode in 1-bit units with the port mode register 5 (pm5). reset input sets port 5 to input mode. figure 4-7 shows a block diagram of port 5. figure 4-7: p50 to p57 configurations remarks: 1. puo : pull-up resistor option register 2. pm : port mode register 3. rd : port 5 read signal 4. wr : port 5 write signal wr pm wr port rd selector output latch (p50 to p57) pm50 to pm57 internal bus pm50 to pm57 p50 to p57 p-ch wr puo v dd pu50 to pu57 85 chapter 4 port functions user?s manual u15251ee4v0ud00 4.2.6 port 6 port 6 is an 8-bit input/output port with output latches. input mode/output mode can be specified in 1-bit units with the port mode register 6 (pm6). when pins p60 to p67 are used as input port pins, an on-chip pull-up resistor can be connected bit-wise with the pull-up resistor option register (pu6). the dual-functions include the timer capture input signal. reset input sets port 6 to input mode. figure 4-8 shows block diagram of port 6. figure 4-8: p60 to p67 configurations remarks: 1. puo : pull-up resistor option register 2. pm : port mode register 3. rd : port 6 read signal 4. wr : port 6 write signal wr pm wr port rd selector output latch (p60 to p67) pm60 to pm67 internal bus p60/ti20, p61/ti21, p62/ti22, p63, p64, p65/sck3, p66/so3/sio3, p67/si3 p-ch wr puo v dd pu60 to pu67 86 chapter 4 port functions user?s manual u15251ee4v0ud00 4.2.7 port 7 this is a 2-bit input/output port with output latches. input mode/output mode can be specified in 1-bit units with a port mode register 7. when pins p70 and p71 are used as input port pins, an on-chip pull-up resistor can be connected bit-wise with the pull-up resistor option register (pu7). these pins are dual-function pins and th ey are used as timer input/output signal. reset input sets the input mode. port 7 block diagram is shown in figure 4-9. caution: when used as segment lines, set the port function pf8 according to its functions. figure 4-9: p70, p71 configurations remarks: 1. puo : pull-up resistor option register 2. pm : port mode register 3. rd : port 7 read signal 4. wr : port 7 write signal wr pm wr port rd selector output latch (p70, p71) pm70, pm71 internal bus p70/ti00/to0, p71/ti01 p-ch wr puo v dd pu70, pu71 87 chapter 4 port functions user?s manual u15251ee4v0ud00 4.3 port function control registers the following four types of registers control the ports. port mode registers (pm0, pm2, pm4 to pm7) pull-up resistor option register (pu0, pu2, pu4 to pu7) port function register (pf2) key return mode register (krm) (1) port mode registers (pm0, pm2, pm4 to pm7) these registers are used to set port input/output in 1-bit units. pm0, pm2, pm4 to pm7 are independently set with an 1-bit or an 8-bit memory manipulation instruction. reset input sets registers to ffh. when port pins are used as alternate-function pins, set the port mode register and output latch according to the function. cautions: 1. pins p10 to p14 are input-only pins. 2. as port 0 has an alternate function as external interrupt request input, when the port function output mode is specified and the output level is changed, the inter- rupt request flag is set. when the output mode is used, therefore, the interrupt mask flag should be set to 1 beforehand. 3. the key return mode register specifies p40 to p47 as key return port pins. 88 chapter 4 port functions user?s manual u15251ee4v0ud00 figure 4-10: port mode register format 76543210r/waddress after reset pm0 1 1 1 1 pm03 pm02 pm01 pm00 r/w ff20h ffh 76543210r/waddress after reset pm2 pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 r/w ff22h ffh 76543210r/waddress after reset pm4 pm47 pm46 pm45 pm44 pm43 pm42 pm41 pm40 r/w ff24h ffh 76543210r/waddress after reset pm5 pm57 pm56 pm55 pm54 pm53 pm52 pm51 pm50 r/w ff25h ffh 76543210r/waddress after reset pm6 pm67 pm66 pm65 pm64 pm63 pm62 pm61 pm60 r/w ff26h ffh 76543210r/waddress after reset pm7111111pm71pm70r/wff27hffh pmmn pmmn pin input/output mode selection (m = 0, 2, 4 - 7; n = 0 - 7) 0 output mode (output buffer on) 1 input mode (output buffer off) 89 chapter 4 port functions user?s manual u15251ee4v0ud00 (2) pull-up resistor option regi ster (pu0, pu2, pu4 to pu7) these registers are used to set whether to use an internal pull-up resistor at each port or not. a pull-up resistor is internally used at bits which are set to the input mode at a port where on-chip pull-up resistor use has been specified with pu0, pu2, pu4 to pu7. no on-chip pull-up resistors can be used to the bits set to the output mode, irrespective of pu0, pu2, pu4 to pu7 setting. pu0, pu2, pu4 to pu7 are set with an 1-bit or an 8-bit memory manipulation instruction. reset input sets these registers to 00h. caution: when ports pu0, pu2, pu4 to pu7 pins are used as dual-functions pins, an on-chip pull-up resistor cannot be used even if 1 is set in pum (m = 0, 2, 4 to 7. figure 4-11: pull-up resistor option register (pu0, pu2, pu4 to pu7) format 76543210r/waddress after reset pu0 0 0 0 0 pu03 pu02 pu01 pu00 r/w ff30h 00h 76543210r/waddress after reset pu2 pu27 pu26 pu25 pu24 pu23 pu22 pu21 pu20 r/w ff32h 00h 76543210r/waddress after reset pu4 pu47 pu46 pu45 pu44 pu43 pu42 pu41 pu40 r/w ff34h 00h 76543210r/waddress after reset pu5 pu57 pu56 pu55 pu54 pu53 pu52 pu51 pu50 r/w ff35h 00h 76543210r/waddress after reset pu6 pu67 pu66 pu65 pu64 pu63 pu62 pu61 pu60 r/w ff36h 00h 76543210r/waddress after reset pu7000000pu71pu70r/wff37h00h pumn pumn pin internal pull- up resistor selection (m = 0, 2, 4 - 7; n = 0 - 7) 0 on-chip pull-up resistor not used 1 on-chip pull-up resistor used 90 chapter 4 port functions user?s manual u15251ee4v0ud00 (3) port function register (pf2) this register is used to set the lcd segment function of port 2. pf2 is set with an 1-bit or 8-bit manipulation instruction. reset input sets this register to 00h. figure 4-12: port function register (pf2) format caution: bits 3 to 7 have to be set always to 0. 76543210r/waddress after reset pf2 0 0 0 0 0 pf22 pf21 pf20 r/w ff52h 00h pf2n pf2n port function selection (n = 0 - 2) 0 push pull output buffer 1 n-channel open drain output buffer 91 chapter 4 port functions user?s manual u15251ee4v0ud00 (4) key return mode register (krm) this register is used to enable /disable the key return signalling. krm is set with an 1-bit or 8-bit manipulation instruction. reset input sets this register to 00h. figure 4-13: key return mode register (krm) format 7654321<0>r/waddress after reset krm0000000krr/wff47h00h kr key return mode signalling 0 key return mode disable 1 key return mode enable 92 chapter 4 port functions user?s manual u15251ee4v0ud00 4.4 port function operations port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 writing to input/output port (1) output mode a value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. once data is written to the output latch, it is retained until data is written to the output latch again. (2) input mode a value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. once data is written to the output latch, it is retained until data is written to the output latch again. caution: in the case of 1-bit memory manipulatio n instruction, although a single bit is manipu- lated the port is accessed as an 8-bit unit. therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined except for the manipulated bit. 4.4.2 reading from input/output port (1) output mode the output latch contents are read by a transfer instruction. the output latch contents do not change. (2) input mode the pin status is read by a transfer instruction. the output latch contents do not change. 4.4.3 operations on input/output port (1) output mode an operation is performed on the output latch contents, and the result is written to the output latch. the output latch contents are output from the pins. once data is written to the output latch, it is retained until data is written to the output latch again. (2) input mode the output latch contents are undefined, but since the output buffer is off, the pin status does not change. caution: in the case of 1-bit memory manipulatio n instruction, although a single bit is manipu- lated the port is accessed as an 8-bit unit. therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit. 93 user?s manual u15251ee4v0ud00 chapter 5 clock generator 5.1 clock generator functions the clock generator generates the clock to be supplied to the cpu and peripheral hardware. the following two types of system clock oscillators is available. (1) main system clock oscillator this circuit oscillates at frequenc ies of 4 to 8.38 mhz. oscillation can be stopped by executing the stop instruction or setting the processor clock control register. (2) subsystem clock oscillator the circuit oscillates at a typical frequency of 40 khz. oscillation cannot be stopped. 94 chapter 5 clock generator user?s manual u15251ee4v0ud00 5.2 clock generator configuration the clock generator consists of the following hardware. figure 5-1: block diagram of clock generator table 5-1: clock generator configuration item configuration control register processor clock control register (pcc) oscillator main system clock oscillator subsystem clock oscillator main system clock oscillator x2 x1 stop mcc cls css pcc2 pcc1 internal bus standby control circuit 2 f x 2 2 f x 2 3 f x 2 4 f x prescaler clock to peripheral hardware prescaler f x cpu clock (f cpu ) f x processor clock control register pcc0 3 selector subsystem clock oscillator cl2 cl1 f xt watch timer 2 f xt 1/2 95 chapter 5 clock generator user?s manual u15251ee4v0ud00 5.3 clock generator control register the clock generator is controlled by the processor clock control register (pcc). (1) processor clock control register (pcc) the pcc selects a cpu clock and the division ratio, determines whether to make the main system clock oscillator operate or stop. the pcc is set with an 1-bit or an 8-bit memory manipulation instruction. reset input sets the pcc to 04h. figure 5-2: processor clock control register format (1/2) <7>6<5><4>3210r/waddress after reset pcc mcc 0 cls note ccs 0 pcc2 pcc1 pcc0 r/w fffbh 04h r/wr rr/wrr/wr/wr/w css pcc2 pcc1 pcc0 cpu clock selection (f cpu ) 0 000 f x (0.25 s) 001 f x /2 (0.5 s) 010 f x /2 2 (1 s) 011 f x /2 3 (2 s) 100 f x /2 4 (4 s) 1 000 f xt /2 (122 s) 001 010 011 100 other than above setting prohibited cls cpu clock status 0 main system clock 1 subsystem clock 96 chapter 5 clock generator user?s manual u15251ee4v0ud00 figure 5-2: processor clock control register format (2/2) note: bit 5 is a read-only bit. remark: when the cpu is operating on the subsystem clock, mcc should be used to stop the main system clock oscillation. a stop instruction should not be used. cautions: 1. bit 3 must be set to 0. 2. when external clock input is used mcc should not be set, because the x2 pin is connected to v dd via a resistor. remarks: 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. figures in parentheses indicate minimum instruction execution time: 2 f cpu when operating at f x = 8.0 mhz or f xt = 32.768 khz. mcc main system clock oscillation control 0 oscillation possible 1 oscillation stopped 97 chapter 5 clock generator user?s manual u15251ee4v0ud00 5.4 system clock oscillator 5.4.1 main system clock oscillator the main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 8.0 mhz) connected to the x1 and x2 pins. external clocks can be input to the main system clock oscillator. in this case, input the clock signal to the x1 pin and leave open he x2 pin. figure 5-3 shows an external circuit of the main system clock oscillator. figure 5-3: external circuit of main system clock oscillator (a) crystal and ceramic oscillation (b) external clock caution: do not execute the stop instruction and do not set mcc (bit 7 of processor clock control register pcc) to 1 if an external clock is input. this is because when the stop instruction or mcc is set to 1, the main system clock operation stops and the x2 pin is connected to v dd1 via a pull-up resistor. x2 x1 ic crystal or ceramic resonator external clock x2 x1 open pd74hcu04 98 chapter 5 clock generator user?s manual u15251ee4v0ud00 5.4.2 subsystem clock oscillator the subsystem clock oscillator oscilla tes with a rc-resonator (standard: 40 khz) connected to the cl1 and cl2 pins. external clocks can be input to the subsystem clock osc illator. in this case, input the clock signal to the cl1 pin and leave open he cl2 pin. figure 5-4 shows an external circui t of the subsystem clock oscillator. figure 5-4: external circuit of subsystem clock oscillator (a) rc oscillation (b) external clock cautions: 1. when an external clock is used for can, the cpu operation and the watch timer operation with subsystem clock is prohibited. the setting of the css-bit (pcc-register) and the wtm 7-bit (wtm-register) to 1 is prohibited. 2. when using a main system clock oscillator and a subsystem clock oscillator, carry out wiring in the broken-line area in figures 5-3 and 5-4 as follows to pre- vent any effects from wiring capacities. minimize the wiring length. do not allow wiring to intersect with other signal conductors. do not allow wiring to come near abruptly changing high current. set the potential of the grounding position of the oscillator capacitor to that of v ss . do not ground to any ground pattern where high current is present. do not fetch signals from the oscillator. take special note of the fact that the subsystem clock oscillator is a circuit with low-level amplification so that current consumption is maintained at low levels. figure 5-5 shows examples of oscillator having bad connection. cl1/cclk cl2 r c external clock cl1/cclk cl2 99 chapter 5 clock generator user?s manual u15251ee4v0ud00 figure 5-5: examples of oscillator with bad connection (1/3) (a) wiring of connection circuits is too long (b) a signal line crosses over oscillation circuit lines ic x2 x1 x2 x1 portn (n = 0, 2, 4 to 7) ic 100 chapter 5 clock generator user?s manual u15251ee4v0ud00 figure 5-5: examples of oscillat or with bad connection (2/3) (c) changing high current is too near a signal conductor (d) current flows through the grounding line of the oscillator (potential at points a, b, and c fluctuate) ic x2 x1 high current ic x2 ab c pnm v dd high current x1 101 chapter 5 clock generator user?s manual u15251ee4v0ud00 figure 5-5: examples of oscillator with bad connection (3/3) (e) signals are fetched (f) signal conductors of the main and subsystem clock are parallel and near each other remark: when using a subsystem clock, replace x1 and x2 with cl1 and cl2, respectively. caution: in figure 5-5 (f), cl1 and x1 are wired in parallel. thus, the cross-talk noise of x1 may increase with cl1, resulting in malfunctioni ng. to prevent that from occurring, it is recommended to wire cl1 and x1 so that they are not in parallel, and to connect the ic pin between cl1 and x1 directly to v ss . 5.4.3 when no subsystem clock is used if it is not necessary to use subsystem clocks fo r low power consumption operations and clock opera- tions, connect the cl1 and cl2 pins as follows. cl1: connect to v dd or gnd cl2: open ic x2 x1 ic x2 x1 cl1 cl2 cl1 and cl2 are wiring in parallel 102 chapter 5 clock generator user?s manual u15251ee4v0ud00 5.5 clock generator operations the clock generator generates the following various types of clocks and controls the cpu operating mode including the standby mode. main system clock f x subsystem clock f xt cpu clock f cpu clock to peripheral hardware the following clock generator functions and operations are determined with the processor clock control register (pcc). (a) upon generation of reset signal, the lowest speed mode of the main system clock (4 s when operated at 8.0 mhz) is selected (pcc = 04 h). main system clock oscillation stops while low level is applied to reset pin. (b) with the main system clock selected , one of the five cpu clock stages (f x , f x /2, f x /2 2 , f x /2 3 or f x /2 4 ) can be selected by setting the pcc. (c) with the main system clock selected, two standby modes, the stop and halt modes, are available. (d) the pcc can be used to select the subsystem clock and to operate the system with low cur- rent consumption (122 s when operated at 32.768 khz). (e) with the subsystem clock selected, main system clock oscillation can be stopped with the pcc. the halt mode can be used. however, the stop mode cannot be used. (subsystem clock oscillation c annot be stopped.) 103 chapter 5 clock generator user?s manual u15251ee4v0ud00 5.5.1 main system clock operations when operated with the main system clock (with bit 5 (cls) of the processor clock control register (pcc) set to 0), the following operations are carried out by pcc setting. (a) because the operation guarantee instruction execution speed depends on the power supply voltage, the instruction execution time can be changed by bits 0 to 2 (pcc0 to pcc2) of the pcc. (b) if bit 7 (mcc) of the pcc is set to 1 when op erated with the main system clock, the main sys- tem clock oscillation does not stop. when bit 4 (css) of the pcc is set to 1 and the operation is switched to subsystem clock operation (cls = 1) after that, the main system clock oscilla- tion stops (see figure 5-6). figure 5-6: main system clock stop function (a) operation when mcc is set after setting css with main system clock operation 5.5.2 subsystem clock operations when operated with the subsystem clock (with bit 5 (cls) of the processor clock control register (pcc) set to 1), the following operations are carried out. (a) the instruction execution time remains constant (122 s when operated at 32.768 khz) irre- spective of bits 0 to 2 (pcc0 to pcc2) of the pcc. (b) watchdog timer counting stops. caution: do not execute the stop instruction while the subsystem clock is in operation. mcc css cls main system clock oscillation subsystem clock oscillation cpu clock 104 chapter 5 clock generator user?s manual u15251ee4v0ud00 5.6 changing system clock and cpu clock settings 5.6.1 time required for switchover between system clock and cpu clock the system clock and cpu clock can be switched over by means of bit 0 to bit 2 (pcc0 to pcc2) and bit 4 (css) of the processor clock control register (pcc). the actual switchover operation is not performed directly after writing to the pcc, but operation contin- ues on the pre-switchover clock for several instructions (see table 5-2). determination as to whether the system is operati ng on the main system clock or the subsystem clock is performed by bit 5 (cls) of the pcc register. caution: selection of the cpu clock cycle scaling factor (pcc0 to pcc2) and switchover from the main system clock to the subsystem clock (changing css from 0 to 1) should not be performed simultaneously. simultaneous setting is possible, however, for selec- tion of the cpu clock cycle scaling factor (pcc0 to pcc2) and switchover from the subsystem clock to the main system clock (changing css from 1 to 0). remarks: 1. one instruction is the minimum instruction execution time with the pre-switchover cpu clock. 2. figures in parentheses apply to operation with f x = 8.0 mhz and f xt = 32.768 khz. table 5-2: maximum time required for cpu clock switchover set values after switchover set values before switchover css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 00 0 000 0 100 1 000 1 101 0 01x x x 0 0 0 0 8 instructions 4 instructions 2 instructions 1 instruction 1 instruction 0 0 1 16 instructions 4 instructions 2 instructions 1 instruction 1 instruction 0 1 0 16 instructions 8 instructions 2 instructions 1 instruction 1 instruction 0 1 1 16 instructions 8 instructions 4 instructions 1 instruction 1 instruction 1 0 0 16 instructions 8 instructions 4 instructions 2 instructions 1 instruction 1x x x f x /2f xt instruction (77 instructions) f x /4f xt instruction (39 instructions) f x /8f xt instruction (20 instructions) f x /16f xt instruction (10 instructions) f x /32f xt instruction (5 instructions) 105 chapter 5 clock generator user?s manual u15251ee4v0ud00 5.6.2 system clock and cpu clock switching procedure this section describes switching procedure between system clock and cpu clock. figure 5-7: system clock and cpu clock switching (1) the cpu is reset by setting the reset signal to low level after power-on. after that, when reset is released by setting the reset signal to high level, main system clock starts oscillation. at this time, oscillation stabilization time (2 17 /f x ) is secured automatically. after that, the cpu starts executing the instruction at the minimum speed of the main system clock (4 s when operated at 8.0 mhz). (2) after the lapse of a sufficient time for the v dd voltage to increase to enable operation at maximum speeds, the processor clock control register (pcc) is rewritten and the maximum-speed operation is carried out. (3) upon detection of a decrease of the v dd voltage due to an interrupt request signal, the main sys- tem clock is switched to the subsystem clock (whi ch must be in an oscillation stable state). (4) upon detection of v dd voltage reset due to an interrupt request signal, 0 is set to bit 7 (mcc) of pcc and oscillation of the main sys tem clock is started. after the lapse of time required for stabili- zation of oscillation, the pcc is rewritten and the maximum-speed operation is resumed. caution: when subsystem clock is being operated while main system clock was stopped, if switching to the main system clock is made again, be sure to switch after securing oscillation stable time by software. v dd reset interrupt request signal systemclock cpuclock wait (16.3 ms: 8.0 mhz) internal reset operation minimum speed operation maximum speed operation subsystem clock operation f x f x f xt f x high-speed operation 106 user?s manual u15251ee4v0ud00 [memo] 107 user?s manual u15251ee4v0ud00 chapter 6 main clock monitor 6.1 main clock monitor function the main clock monitor task is, to watch the activiti es of the main system clock by using the subsystem clock. if the main clock fails for more than three sub clock cycles, the main clock monitor detects the fault condition and triggers the chip reset. the following procedure allows the using of the main clock monitor: (1) main system clock is working. (2) subsystem clock is working. (3) enable the main system clock monitor by setting the clme bit to 1. cautions: 1. the main clock monitor is automatically disabled, if the cpu is in stop mode, or the cpu is clocked by the subsystem clock and mcc is set to 1. 2. once the main clock monitor has been enabled, it can only disabled by triggering the external reset. 108 chapter 6 main clock monitor user?s manual u15251ee4v0ud00 6.2 main clock monitor circuit configuration the main clock monitor consists of the following hardware. figure 6-1: main clock monitor circuit block diagram table 6-1: main clock monitor configuration item configuration control register clock monitor mode register (clm) rising edge detection circuit falling edge detection circuit stop mcc-bit reset periodical latch reset enable clear clear 0 0 0 0 0 0 0 0 clme clock monitor mode register fx fx t 109 chapter 6 main clock monitor user?s manual u15251ee4v0ud00 6.3 main clock monitor control register the following register is used to control the main clock monitor. clock monitor mode register. (1) clock monitor mode register (clm) this register ends the main clock monitor. clm is set with an 1-bit or an 8-bi t memory manipulation instruction. reset input sets clm to 00h. figure 6-2: format clock monitor mode register (clm) 76543210r/waddress after reset clm0000000clmer/wff77h00h clme clock monitor operation selection 0 clock monitor disable 1 clock monitor enable 110 chapter 6 main clock monitor user?s manual u15251ee4v0ud00 6.4 operating modes (1) stop mode release by interrupt when the cpu works on the main system clock and the main system clock oscillator is stopped by the mcc-bit or the stop instruction the clock monitor is disabled. an interrupt wakes up the oscil- lator and after the finished osc illation stabilization time (based on the setting of the osts register) the clock monitor is enabled and the cpu starts working again. the sub clock keeps on running. (2) release by reset when the cpu works on the main system clock and the main system clock oscillator is stopped by the mcc-bit or the stop instruction the clock monitor is disabled. an external reset wakes up the oscillator and clears the clock monitor enable bit. after th e finished oscillation stabilization time (based on the setting of the osts register) the cpu starts working again. the sub clock keeps on running. (3) main clock stopped, sub clock operating, cpu works on sub clock when the cpu works on the subsystem clock and th e main oscillator is st opped by the mcc-bit or the stop instruction the clock monitor is disabled . when the main oscillator is restarted by cpu (via clear of the mcc-bit in pcc register) the clock monitor will be enabled again when the cpu switches from the sub clock to the main system clock after the cpu has got at least 83 main sys- tem clocks in minimum. the application software has to take care of a delay time before switching to the main system clock. the sub clock keeps on running. (4) main clock stopped, sub clock operating, cpu in stop mode on sub clock when the main system clock oscillator is stopped, the cpu works on the sub system clock and the cpu is then set to stop mode by the stop instruction the clock monitor is disabled. this mode can only be released by reset, where a release by an interrupt is not possible. the sub clock keeps on running. (5) main clock operating, sub clock operating, cpu in halt mode on sub clock when the cpu works on the subsystem clock, the ma in oscillator is running and the cpu is set to halt mode and woken up via interrupt the clock monitor continues working the whole time. (6) main clock stopped, sub clock operating, cpu in halt mode on sub clock the clock monitor is disabled when the main cloc k oscillator is switched off and will be enabled when the cpu is running again on main system clock oscillator after the cpu has got at least 83 main system clocks in minimum. the following conditions are valid: the cpu works on the subsystem clock. the main system clock osc illator is stopped via the mcc-bit of the pcc register. the cpu is finally stopped via the halt instruction. wake up is done via an interrupt. the application software has to take care of a delay time before switching to the main system clock. 111 user?s manual u15251ee4v0ud00 chapter 7 16-bit timer 0 7.1 16-bit timer/event counter function 16-bit timer/event counter 0 (tm0) has the following functions: interval timer ppg output pulse width measurement external event counter square wave output (1) interval timer when 16-bit timer/event counter is used as an interval timer, it generates an interrupt request at predetermined time intervals. (2) ppg output 16-bit timer/event counter can output a square wave whose frequency and output pulse width can be freely set. (3) pulse width measurement 16-bit timer/event counter can be used to measure the pulse width of a signal input from an exter- nal source. (4) external event counter 16-bit timer/event counter can be used to measure the number of pulses of a signal input from an external source. (5) square wave output 16-bit timer/event counter can output a square wave any frequency. 112 chapter 7 16-bit timer 0 user?s manual u15251ee4v0ud00 7.2 16-bit timer/event counter 0 configuration 16-bit timer/event counter 0 (tm0) consists of the following hardware: figure 7-1: block diagram of 16-bit timer/event counter 0 (tm0) table 7-1: configuration of 16-bit timer/event counter (tm0) item configuration timer register 16 bits x 1 (tm0) register capture/compare register: 16 bits u 2 (cr00, cr01) timer output 1 (to0) control register 16-bit timer mode control register (tmc0) capture/compare register 0 (crc0) 16-bit timer output control register (toc0) prescaler mode register 0 (prm0) port mode register 7 (pm7) internal bus crc02 crc01 crc00 capture/compare control register 0 (crc0) ti01/ p71 ti00/ to0/ p70 noise rejection circuit 16-bit capture/compare register 00 (cr00) 16-bit timer register (tm0) 16-bit capture/compare register 01 (cr01) noise rejection circuit clear coincidence coincidence to0/p70/ti00 inttm00 output control circuit inttm01 crc02 2 prescaler mode register 0 (prm0) timermode control register (tmc0) timer output control register (toc0) internal bus selector selector selector prm01 prm00 ovf0 tmc01 tmc02 tmc03 toe0 toc01 lvr0 lvs0 toc04 ospe ospt selector noise rejection circuit fx/2 1 fx/2 4 fx/2 7 fx/2 113 chapter 7 16-bit timer 0 user?s manual u15251ee4v0ud00 (1) 16-bit timer register (tm0) tm0 is a 16-bit read-only register that counts pulses. the counter is incremented in synchronization with the rising edge of an input clock. if the count value is read during operation, input of the count clock is temporarily stopped, and the count value at that point is read. the count value is reset to 0000h in the following cases: <1> reset is input. <2> tmc03 and tmc02 are cleared. <3> valid edge of ti00 is input in the clear & start mode by inputting valid edge of ti00. <4> tm0 and cr00 coincide with each other in the clear & start mode on coincidence between tm0 and cr00. 114 chapter 7 16-bit timer 0 user?s manual u15251ee4v0ud00 (2) capture/compare register 00 (cr00) cr00 is a 16-bit register that functions as a capture register and as a compare register. whether this register functions as a capture or compare register is specified by using bit 0 (crc00) of the capture/compare control register 0. (a) when using cr00 as compare register the value set to cr00 is always compared with the count value of the 16-bit timer register (tm0). when the values of the two coincide, an interrupt request (inttm00) is generated. when tm00 is used as an interval timer, cr00 can also be used as a register that includes the interval time. (b) when using cr00 as capture register the valid edge of the ti00 or ti01 pin can be selected as a capture trigger. the valid edge of ti00 and ti01 is performed via the prescaler mode register 0 (prm0). tables 7-2 and 7-3 show the conditions that apply when the capture trigger is specified as the valid edge of the ti00 pin and the valid edge of the ti01 pin respectively. cr00 is set by a 16-bit memory manipulation instruction. after reset input, the value of cr00 is undefined. caution: set another value than 0000h to cr00. this means, that an 1-pulse count operation cannot be performed when cr00 is used as an event counter. table 7-2: valid edge of ti00 pin and valid edge of capture trigger of capture/compare register es01 es00 valid edge of ti00 pin capture trigger of cr00 capture trigger of cr01 0 0 falling edge rising edge falling edge 0 1 rising edge falling edge rising edge 1 0 setting prohibited setting prohibited setting prohibited 11 both rising and falling edges no capture operation both rising and falling edges table 7-3: valid edge of ti01 pin and valid edge of capture trigger of capture/compare register es01 es00 valid edge of ti01 pin capture trigger of cr00 0 0 falling edge rising edge 0 1 rising edge falling edge 1 0 setting prohibited setting prohibited 1 1 both rising and falling edges both rising and falling edges 115 chapter 7 16-bit timer 0 user?s manual u15251ee4v0ud00 (3) capture/compare register 01 (cr01) this is a 16-bit register that can be used as a capture register and a compare register. whether it is used as a capture register or compare register is specified by bit 2 (crc02) of the capture/com- pare control register 0. (a) when using cr01 as compare register the value set to cr01 is always compared with the count value of the 16-bit timer register (tm0). when the values of the two coincide, an interrupt request (inttm01) is generated. (b) when using cr01 as capture register the valid edge of the ti00 pin can be selected as a capture trigger. the valid edge of ti00 is spec- ified by using the prescaler mode register 0 (prm0). r01 is set by a 16-bit memo ry manipulation instruction. after reset input, the value of cr00 is undefined. caution: set another value than 0000h to cr01. this means, that an 1-pulse count operation cannot be performed when cr01 is used as an event counter. 116 chapter 7 16-bit timer 0 user?s manual u15251ee4v0ud00 7.3 16-bit timer/event counter 0 control register the following four types of registers control 16-bit timer/event counter 0. 16-bit timer mode control register (tmc0) capture/compare control register (crc0) 16-bit timer output control register (toc0) prescaler mode register 0 (prm0) port mode register 7 (pm7) (1) 16-bit timer mode control register (tmc0) this register specifies the operation mode of the 16-bit timer and the clear mode, output timing, and overflow detection of the 16-bit timer register. tmc0 is set by an 1-bit or an 8-bit memory manipulation instruction. reset input sets tmc0 to 00h. caution: the 16-bit timer register starts operat ing when a value other than 0, 0 (operation stop mode) is set to tmc02 and tmc03. to stop the operation, set 0, 0 to tmc02 and tmc03. 117 chapter 7 16-bit timer 0 user?s manual u15251ee4v0ud00 figure 7-2: format of 16-bit timer mode control register (tmc0) cautions: 1. before changing the clear mode and to0 output timing, be sure to stop the timer operation (reset tmc02 and tmc03 to 0, 0). 2. the valid edge of the ti00 pin is selected by using the prescaler mode register 0 (prm0). 3. when a mode in which the timer is cleared and started on coincidence between tm0 and cr00, the ovf0 flag is set to 1 when the count value of tm0 changes from ffffh to 0000h with cr00 set to ffffh. remark: t00 : output pin of 16-bit timer/counter (tm0) ti00 : input pin of 16-bit timer/counter (tm0) tm0 : 16-bit timer register cr00 : compare register 00 cr01 : compare register 01 (2) capture/compare cont rol register 0 (crc0) this register controls the operation of the capture/compare registers (cr00 and cr01). 7654321<0>r/waddress after reset tmc0 0 0 0 0 tmc03 tmc02 tmc01 ovf0 r/w ff60h 00h tmc03 tmc02 tmc01 operating mode, clear mode selection of to0 output timing generation of interrupt 000 operation stop (tm0 is cleared to 0) not affected does not generate 001 010 free-running mode coincidence between tm0 and cr00 or coincidence between tm0 and cr01 generates on coincidence between tm0 and cr00 or coincidence between tm0 and cr01 011 coincidence between tm0 and cr00, coincidence between tm0 and cr01, or valid edge of ti00 100 clears and starts at valid edge of ti00 - 101 - 110 clears and starts on coinci- dence between tm0 and cr00 coincidence between tm0 and cr00 or coincidence between tm0 and cr01 111 coincidence between tm0 and cr00, coincidence between tm0 and cr01, or valid edge of ti00 ovf0 detection of overflow of 16-bit timer register 0 overflows 1 does not overflow 118 chapter 7 16-bit timer 0 user?s manual u15251ee4v0ud00 crc0 is set by an 1-bit or an 8-bi t memory manipulation instruction. reset input sets crc0 to 00h. figure 7-3: format of capture/compare control register 0 (crc0) cautions: 1. before setting crc0, be sure to stop the timer operation. 2. when the mode in which the timer is cleared and started on coincidence between tm0 and cr00 is selected by the 16-bit timer mode control register (tmc0), do not specify crc00 as a capture register. 3. if valid edge of ti00 is both falling an d rising, the capture op eration is not avail- able when crc01 = 1. 4. to surely perform the capture operation, the capture trigger requires a pulse two times longer than the count clock selected by prescaler mode register 0 (prm0). 76543210r/waddress after reset crc0 0 0 0 0 0 crc02 crc01 crc00 r/w ff62h 00h crc02 selection of operation mode of cr01 0 operates as compare register 1 operates as capture register crc01 selection of capture trigger of cr00 0 captured at valid edge of ti01 1 captured in reverse phase of valid edge of ti00 crc00 selection of operation mode of cr00 0 operates as compare register 1 operates as capture register 119 chapter 7 16-bit timer 0 user?s manual u15251ee4v0ud00 (3) 16-bit timer output control register (toc0) this register controls the operation of the 16-bit timer/event counter 0 output control circuit by set- ting or resetting the r-s flip-flop, enabling or disabling reverse output, enabling or disabling output of 16-bit timer/counter (tm0), enabling or disabling one-shot pulse output operation, and selecting an output trigger for an one-shot pulse by software. toc0 is set by an 1-bit or an 8-bit memory manipulation instruction. reset input sets toc0 to 00h. figure 7-4 shows the format of toc0. figure 7-4: format of 16-bit timer output control register (toc0) cautions: 1. before setting toc0, be sure to stop the timer operation. 2. lvs0 and lvr0 are 0 when read after data have been set to them. 3. ospt is 0 when read because it is automatically cleared after data has been set. 7654<3><2>1<0>r/waddress after reset toc0 0 0 0 toc04 lvs0 lvr0 toc01 toe0 r/w ff63h 00h toc04 timer output f/f control on coincidence between cr01 and tm0 0 disables inversion timer output 1 enables inversion timer output lvs0 lvr0 set status of timer output f/f of 16-bit timer/counter (tm0) 0 0 not affected 0 1 resets timer output f/f (0) 1 0 sets timer output f/f (1) 1 1 setting prohibited toc01 timer output f/f control on coincidence between cr00 and tm0 0 disables inversion timer output f/f 1 enables inversion timer output f/f toe0 output control of 16- bit timer/counter (tm0) 0 disables output (port mode) 1 enables output 120 chapter 7 16-bit timer 0 user?s manual u15251ee4v0ud00 (4) prescaler mode register 0 (prm0) this register selects a count clock of the 16-bit timer/event counter 0 and the valid edge of ti00, ti01 input. prm0 is set by an 1-bit or an 8-bit memory manipulation instruction. reset input sets prm0 to 00h. figure 7-5: format of prescaler mode register 0 (prm0) caution: when selecting the valid edge of ti00 as the count clock, do not specify the valid edge of ti00 to clear and start the timer and as a capture trigger. remark: figures in parentheses apply to operation with f x = 8.00 mhz. 76543210r/waddress after reset prm0 es11 es10 es01 es00 0 0 prm01 prm00 r/w ff61h 00h es11 es10 selection of valid edge of ti01 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es01 es00 selection of valid edge of ti00 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges prm01 prm00 selection of count clock 00 f x /2 1 (4 mhz) 01 f x /2 4 (500 khz) 10 f x /2 7 (62.5 khz) 1 1 valid edge of ti00 121 chapter 7 16-bit timer 0 user?s manual u15251ee4v0ud00 (5) port mode register 7 (pm7) this register sets port 7 input/output in 1-bit units. when using the p70/to0/ti00 pin for timer output, set pm70 and the output latch of p70 to 0. pm7 is set with an 1-bit or an 8-bit memory manipulation instruction. reset input sets pm7 value to ffh. figure 7-6: port mode register 7 (pm7) format 76543210r/waddress after reset pm7111111pm71pm70r/wff27hffh pm7n p0n pin input/output mode selection (n = 0, 1) 0 output mode (output buffer on) 1 input mode (output buffer off) 122 chapter 7 16-bit timer 0 user?s manual u15251ee4v0ud00 7.4 16-bit timer/event counter 0 operations 7.4.1 operation as interval timer (16 bits) the 16-bit timer/event counter operates as an interval timer when the 16-bit timer mode control register (tmc0) and capture/compare control register 0 (crc0) are set as shown in figure 7-7. in this case, 16-bit timer/event counter repeatedly generates an interrupt at the time interval specified by the count value set in advance to the 16-bit capture/compare register 00 (cr00). when the count value of the 16-bit timer register 0 (tm0) coincides with the set value of cr00, the value of tm0 is cleared to 0, and the timer continues counting. at the same time, an interrupt request signal (inttm00) is generated. the count clock of the 16-bit timer/event counter 0 can be selected by bits 0 and 1 (prm00 and prm01) of the prescaler mode register 0 (prm0). figure 7-7: control register settings when timer 0 operates as interval timer (a) 16-bit timer mode control register (tmc0) (b) capture/compare cont rol register 0 (crc0) remark: 0/1: when these bits are reset to 0 or set to 1, the other functions can be used along with the interval timer function. for details, refer to figures 7-2 and 7-3. 0000 tmc03 1 tmc02 1 tmc01 0/1 ovf0 0 tmc0 clears and starts on coincidence between tm0 and cr00. 00000 crc02 0/1 crc01 0/1 crc00 0 crc0 cr00 as compare register 123 chapter 7 16-bit timer 0 user?s manual u15251ee4v0ud00 figure 7-8: configuration of interval timer figure 7-9: timing of interval timer operation remark: interval time = (n+1) x t: n = 0000h to ffffh fx/2 1 fx/2 4 fx/2 7 ti00/p70 selector 16-bit capture/compare register 00 (cr00) 16-bit timer register (tm0) ovf0 clear circuit inttm00 count starts clear clear interrupt accepted interrupt accepted t 0000h 0001h n 0000h 0001h n 0000h 0001h n n n n n interval time interval time interval time count clock tm0 count value cr00 inttm00 to0 124 chapter 7 16-bit timer 0 user?s manual u15251ee4v0ud00 7.4.2 ppg output operation the 16-bit timer/counter can be used for ppg (programmable pulse generator) output by setting the 16-bit timer mode control register (tmc0) and capture/compare control register 0 (crc0) as shown in figure 7-10. the ppg output function outputs a rectangular wave with a cycle sp ecified by the count value set in advance to the 16-bit capture/compare register 00 (cr00) and a pulse width specified by the count value set in advance to the 16-bit capture/compare register 01 (cr01). figure 7-10: control register settings in ppg output operation (a) 16-bit timer mode control register (tmc0) (b) capture/compare cont rol register 0 (crc0) (c) 16-bit timer output control register (toc0) remark: x: don?t care cautions: 1. make sure that 0000h d cr01 < cr00 d ffffh is set to cr00 and cr01. 2. the cycle of the pulse generator through ppg output (cr00 setting value +1) has a duty of (cr01 setting value + 1) / (cr00 setting value + 1) 0000 tmc03 1 tmc02 1 tmc01 0 ovf0 0 tmc0 clears and starts on coincidence between tm0 and cr00. 00000 crc02 0 crc01 crc00 0 crc0 cr00 as compare register cr01 as compare register x 000 toc04 1 lvs0 0/1 lvr0 0/1 toc01 1 toe0 1 toc0 enables to0 output reverses output on coincidence between tm0 and cr01 specifies initial value of to0 output f/f reverses output on coincidence between tm0 and cr00 125 chapter 7 16-bit timer 0 user?s manual u15251ee4v0ud00 7.4.3 pulse width measurement the 16-bit timer register (tm0) can be used to measur e the pulse widths of the signals input to the ti00 and ti01 pins. measurement can be carried out with tm0 used as a free running counter or by restarting the timer in synchronization with the edge of the signal input to the ti00 pin. (1) pulse width measurement with free running counter and one capture register if the edge specified by the prescaler mode register 0 (prm0) is input to the ti00 pin when the 16- bit timer register (tm0) is used as a free running counter (refer to figure 7-11), the value of tm0 is loaded to the 16-bit capture/compare register 01 (cr01), and an external interrupt request signal (inttm01) is set. the edge is specified by using bits 6 and 7 (es10 and es11) of the prescaler mode register 0 (prm0). the rising edge, falling edge, or both the rising and falling edges can be selected. the valid edge is detected through sampling at a count clock cycle selected by the prescaler mode register 0n (prm0), and the capture operation is not performed until the valid level is detected two times. therefore, noise with a short pulse width can be rejected. figure 7-11: control register settings for pulse width measurement with free running counter and one capture register (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) remark: 0/1: when these bits are reset to 0 or set to 1, the other functions can be used along with the pulse width measurement function. for details, refer to figures 7-2 and 7-3. 0000 tmc03 0 tmc02 1 tmc01 0/1 ovf0 0 tmc0 free running mode 00000 crc02 1 crc01 0/1 crc00 0 crc0 cr00 as compare register cr01 as capture register 126 chapter 7 16-bit timer 0 user?s manual u15251ee4v0ud00 figure 7-12: configuration for pulse widt h measurement with free running counter figure 7-13: timing of pulse width measurement with free running counter and one capture register (with both edges specified) inttm00 fx/2 1 fx/2 4 fx/2 7 selector 16-bit capture/compare register 01 (cr01) 16-bit timer register (tm0) ovf0 ti00/p70 internal bus t (d1 - d0) x t (10000h - d1 + d2) x t (d3 - d2) x t count clock 0000h 0001h d0 d1 0000h d2 d3 tm0 count value d3 ti00 pin input value loaded to cr01 inttm00 ovf0 d0 d1 d2 ffffh 127 chapter 7 16-bit timer 0 user?s manual u15251ee4v0ud00 (2) measurement of two pulse widths with free running counter the pulse widths of the two signals respectively input to the ti00 and ti01 pins can be measured when the 16-bit timer register (tm0) is used as a free running counter (refer to figure 7-14). when the edge specified by bits 4 and 5 (es00 and es01) of the prescaler mode register 0 (prm0) is input to the ti00 pin, the value of the tm0 is loaded to the 16-bit capture/compare reg- ister 01 (cr01) and an external interrupt request signal (inttm01) is set. when the edge specified by bits 6 and 7 (es10 and es11) of the prescaler mode register 0 (prm0) is input to the ti01 pin, the value of tm0 is loaded to the 16-bit capture/compare register 00 (cr00), and an external interrupt request signal (inttm00) is set. the edges of the ti00 and ti01 pins are specified by bits 4 and 5 (es00 and es01) and bits 6 and 7 (es10 and es11) of prm0, respectively. the risi ng, falling, or both risi ng and falling edges can be specified. the valid edge of ti00 pin and ti01 pin is detected through sampling at a count clock cycle selected by the prescaler mode register 0 (prm0), and the capture operation is not performed until the valid level is detected two times. therefore, noise with a short pulse width can be rejected. figure 7-14: control register settings for measurement of two pulse widths with free running counter (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) remark: 0/1: when these bits are reset to 0 or set to 1, the other functions can be used along with the pulse width measurement function. for details, refer to figures 7-2 and 7-3. 0000 tmc03 0 tmc02 1 tmc01 0/1 ovf0 0 tmc0 free running mode 00000 crc02 1 crc01 0 crc00 1 crc0 cr00 as capture register captures valid edge of ti01/p71 pin to cr00. cr01 as capture register 128 chapter 7 16-bit timer 0 user?s manual u15251ee4v0ud00 (a) capture operation (free running mode) the following figure illustrates th e operation of the capture regist er when the ca pture trigger is input. figure 7-15: cr01 capture operation with rising edge specified figure 7-16: timing of pulse width measurement operation with free running counter (with both edges specified) count clock tm0 ti00 rising edge detection cr01 inttm01 n?3 n?2 n?1 n n+1 n t 0000h 0000h ffffh 0001h d0 d0 ti01 pin input cr00 capture value inttm01 inttm00 ovf0 (d1 ? d0) 129 chapter 7 16-bit timer 0 user?s manual u15251ee4v0ud00 (3) pulse width measurement with free running counter and two capture registers when the 16-bit timer register (tm0) is used as a free running counter (refer to figure 7-17), the pulse width of the signal input to the ti00 pin can be measured. when the edge specified by bits 4 and 5 (es00 and es01) of the prescaler mode register 0 (prm0) is input to the ti00 pin, the value of tm0 is loaded to the 16-bit capture/compare register 01 (cr01), and an external interrupt request signal (inttm01) is set. the value of tm0 is also loaded to the 16-bit capture/compare register 00 (cr00) when an edge reverse to the one that triggers capturing to cr01 is input. the edge of the ti00 pin is specified by bits 4 and 5 (es00 and es01) of the prescaler mode reg- ister 0 (prm0). the rising or falling edge can be specified. the valid edge of ti00 pin and ti01 pin is detected through sampling at a count clock cycle selected by the prescaler mode register 0 (prm0), and the capture operation is not performed until the valid level is detected two times. therefore, noise with a short pulse width can be rejected. caution: if the valid edge of the ti00 pin is specified to be both the rising and falling edges, the capture/compare register 00 (cr00) cannot perform its capture operation. figure 7-17: control register settings for pulse width measurement with free running counter and two capture registers (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) remark: 0/1: when these bits are reset to 0 or set to 1, the other functions can be used along with the pulse width measurement function. for details, refer to figures 7-2 and 7-3. 0000 tmc03 0 tmc02 1 tmc01 0/1 ovf0 0 tmc0 free running mode 00000 crc02 1 crc01 1 crc00 1 crc0 cr00 as capture register captures to cr00 at edge reverse to valid edge o f ti00 pin. cr01 as capture register 130 chapter 7 16-bit timer 0 user?s manual u15251ee4v0ud00 figure 7-18: timing of pulse width measurement with free running counter and two capture registers (with rising edge specified) t (d1 - d0) x t (10000h - d1 + d2) x t count clock 0000h 0001h d0 d1 ffffh 0000h d2 d3 tm0 count value d0 d2 d3 ti00 pin input d1 (d3 - d2) x t inttm01 ovf0 cr01 capture value cr00 capture value 131 chapter 7 16-bit timer 0 user?s manual u15251ee4v0ud00 (4) pulse width measurement by restarting when the valid edge of the ti00 pin is detected, the pulse width of the signal input to the ti00 pin can be measured by clearing the 16-bit timer register (tm0) once and then resuming counting after loading the count value of tm0 to the 16-bit capture/compare register 01 (cr01). the edge of the ti00 pin is specified by bits 4 and 5 (es00 and es01) of prm0. the rising or fall- ing edge can be specified. the valid edge is detected through sampling at a count clock cycle selected by the prescaler mode register 0 (prm0), and the capture operation is not performed until the valid level is detected two times. therefore, noise with a short pulse width can be rejected. caution: if the valid edge of the ti00 pin is specified to be both the rising and falling edges, the capture/compare register 00 (cr00) cannot perform its capture operation. figure 7-19: control register settings for pulse width measurement by restarting (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) remark: 0/1: when these bits are reset to 0 or set to 1, the other functions can be used along with the pulse width measurement function. for details, refer to figures 7-2 and 7-3. 0000 tmc03 1 tmc02 0 tmc01 0/1 ovf0 0 tmc0 clears and starts at valid edge of ti00/p70 pin. 00000 crc02 1 crc01 1 crc00 1 crc0 ncr00 as capture register captures to cr00 at edge reverse to valid edge of ti00/p70. cr01 as capture register 132 chapter 7 16-bit timer 0 user?s manual u15251ee4v0ud00 figure 7-20: timing of pulse width measuremen t by restarting (with rising edge specified) t d1 x 1 d2 x 1 count clock 0000h 0001h d0 d1 0000h 0001h d2 0001h tm0 count value d0 d2 ti00 pin input d1 inttm01 0000h cr01 capture value cr00 capture value 133 chapter 7 16-bit timer 0 user?s manual u15251ee4v0ud00 7.4.4 operation as external event counter 16-bit timer/event counter can be used as an external event counter which counts the number of clock pulses input to the ti00 pin from an external source by using the 16-bit timer register (tm0). each time the valid edge specified by the prescaler mode register 0 (prm0) has been input to the ti00 pin, tm0 is incremented. when the count value of tm0 coincides with the value of the 16-bit capture/compare register 00 (cr00), tm0 is cleared to 0, and an interrupt request signal (inttm00) is generated. the edge of the ti00 pin is specified by bits 4 and 5 (es00 and es01) of the prescaler mode register 0 (prm0). the rising, falling, or both the rising and falling edges can be specified. the valid edge is detected through sampling at a coun t clock cycle, selected by the prescaler mode reg- ister 0 (prm0) and performed until the valid level is detected two times. therefore, noise with a short pulse width can be rejected. figure 7-21: control register settings in external event counter mode (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) remark: 0/1: when these bits are reset to 0 or set to 1, the other functions can be used along with the external event counter function. for details, refer to figures 7-2 and 7-3. 0000 tmc03 1 tmc02 1 tmc01 0/1 ovf0 0 tmc0 clears and starts on coincidence between tm0 and cr00 00000 crc02 0/1 crc01 0/1 crc00 0 crc0 cr00 as compare register 134 chapter 7 16-bit timer 0 user?s manual u15251ee4v0ud00 figure 7-22: configuration of external event counter figure 7-23: timing of external event counter operation (with rising edge specified) caution: read tm0 when reading the count value of the external event counter. 16-bit capture/compare register (cr00) 16-bit timer register (tm0) clear ovf0 inttm00 16-bit capture/compare register 01 (cr01) valid edge of ti00 internal bus noise elimination circuit selector fx/2 fx/2 1 fx/2 4 fx/2 7 noise elimination circuit ti00 pin input 0000h 0001h 0003h 0005h n - 1 0001h 0003h tm0 count value n cr00 inttm00 0002h 0004h 0000h 0002h n 135 chapter 7 16-bit timer 0 user?s manual u15251ee4v0ud00 7.4.5 operation to output square wave the 16-bit timer/event counter 0 can be used to output a square wave with any frequency at an interval specified by the count value set in advance to the 16-bit capture/compare register 00 (cr00). by setting bits 0 (toe0) and 1 (toc01) of the 16-bit timer output control register to 1, the output status of the to0 pin is reversed at an interval specified by the count value set in advance to cr00. in this way, a square wave of any frequency can be output. figure 7-24: set contents of control registers in square wave output mode (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) (c) 16-bit timer output control register (toc0) remark: 0/1: when these bits are reset to 0 or set to 1, the other functions can be used along with the square wave output function. for details, refer to figures 7-2, 7-3, and 7-4. 0000 tmc03 1 tmc02 1 tmc01 0/1 ovf0 0 tmc0 clears and starts on coincidence between tm0 and cr00. 00000 crc02 0/1 crc01 0/1 crc00 0 crc0 cr00 as compare register 000 toc04 0 lvs0 0/1 lvr0 0/1 toc01 1 toe0 1 toc0 enables to0 output does not reverse output on coincidence between tm0 and cr01 specifies initial value of to0 output f/f reverses output on coincidence between tm0 and cr00 136 chapter 7 16-bit timer 0 user?s manual u15251ee4v0ud00 figure 7-25: timing of square wave output operation 0000h 0001h n - 1 n 0001h 0002h n - 1 n n count clock tm0 count value cr00 0000h 0000h 0002h inttm00 to0 pin output 137 chapter 7 16-bit timer 0 user?s manual u15251ee4v0ud00 7.5 16-bit timer/event counter 0 operating precautions (1) error on starting timer an error of up to 1 clock occurs before the coincidence signal is generated after the timer has been started. this is because the 16-bit timer regi ster (tm0) is started asynchronously in respect to the count pulse. figure 7-26: start timing of 16-bit timer register (2) 16-bit compare register setting set another value than 0000h to the 16-bit captured compare register cr00, cr01. this means, that an 1-pulse count operation cannot be performed, when it is used as event counter. (3) setting compare register during timer count operation if the value to which the current value of the 16-bit capture/compare register 00 (cr00) has been changed is less than the value of the 16-bit time r register (tm0), tm0 continues counting, over- flows, and starts counting again from 0. if the new value of cr00 (m) is less than the old value (n), the timer must be restarted after the value of cr00 has been changed. figure 7-27: timing after changing compare register during timer count operation remark: n > x > m tm0 count value 0000h 0001h 0002h 0004h count pulses timer starts 0003h cr00 nm count pulse tm0 count x - 1 x ffffh 0000h 0001h 0002h 138 chapter 7 16-bit timer 0 user?s manual u15251ee4v0ud00 (4) data hold timing of capture register if the valid edge is input to the ti00 pin while the 16-bit capture/compare register 01 (cr01) is read, cr01 performs the capture operation, but this capture value is not guaranteed. however, the interrupt request flag (inttm01) is set as a result of detection of the valid edge. figure 7-28: data hold timing of capture register (5) setting valid edge before setting the valid edge of the ti00/to0/p70 pin, stop the timer operation by resetting bits 2 and 3 (tmc02 and tmc03) of the 16-bit timer mode control register to 0, 0. set the valid edge by using bits 4 and 5 (es00 and es01) of the prescaler mode register 0 (prm0). tm0 count n n+1 n+2 m m+1 m+2 n+1 x count pulse edge input interrupt request flag capture read signal cr01 interrupt value capture 139 chapter 7 16-bit timer 0 user?s manual u15251ee4v0ud00 (6) operation of ovf0 flag the ovf0 flag is set to 1 in the following case: select mode in which 16-bit timer/counter is cleared and started on coincidence between tm0 and cr00. p set cr00 to ffffh p when tm0 counts up from ffffh to 0000h figure 7-29: operation timing of ovf0 flag (7) contending operations (a) the contending operation between the read time of 16-bit capture/compare register (cr00/cr01) and capture trigger input (cr00/cr01 used as capture register) capture/trigger input is prior to the other. the data read from cr00/cr01 is not defined. (b) the coincidence timing of contending operation between the write period of 16-bit cap- ture/compare register (cr00/cr01) and 16-bit timer register (tm0) (cr00/cr01 used as a compare register) the coincidence discriminant is not performed normally. do not write any data to cr00/cr01 near the coincidence timing. ffffh fffeh ffffh 0000h 0001h count pulse cr00 tm0 ovf0 inttm00 140 chapter 7 16-bit timer 0 user?s manual u15251ee4v0ud00 (8) timer operation (a) even if the 16-bit timer counter 0 (tm0) is read , the value is not captured by 16-bit timer cap- ture/compare register 01 (cr01). (b) regardless of the cpu's operation mode, when the timer stops, the input signals to pins ti00/ti01 are not acknowledged. (9) capture operation (a) if ti00 is specified as the valid edge of the count clock, capture operation by the capture regis- ter specified as the trigger for ti00 is not possible. (b) if both the rising and falling e dges are selected as the valid ed ges of ti00, capture is not per- formed. (c) to ensure the reliability of the capture operation, the capture trigger requires a pulse two times longer than the count clock selected by prescaler mode register 0 (prm0). (d) the capture operation is performed at the fall of the count clock. an interrupt request input (inttm0n), however, is generated at the rise of the next count clock. (10) compare operation (a) the inttm0n may not be generated if the set value of 16-bit timer capture registers 00, 01 (cr00, cr01) and the count value of 16-bit timer counter (tm0) match and cr00 and cr01 are overwritten at the timing of inttm0n generation. therefore, do not overwrite cr00 and cr01 frequently even if overwriting the same value. (b) capture operation may not be performed for cr00/cr01 set in compare mode even if a cap- ture trigger has been input. 141 user?s manual u15251ee4v0ud00 chapter 8 16-bit timer 2 8.1 16-bit timer 2 functions the 16-bit timer 2 (tm2) has the following functions. pulse width measurement divided output of input pulse time stamp function for the dcan figure 8-1 shows 16-bit timer 2 block diagram. figure 8-1: timer 2 block diagram (1) pulse width measurement tm2 can measure the pulse width of an externally input signal. (2) timer stamp function for the dcan an internal signal output of the dcan-module can be used to build a time stamp function of the system (please refer to the chapter of the dcan-module). internal bus internal bus 16-bit timer register (tm2) 16-bit capture register (cr22) edge detection circuit es01, es00 es11, es10 es21, es20 16-bit capture register (cr21) 16-bit capture register (cr20) intovf inttm22 inttm21 inttm20 es21 es20 es11 fx/8 fx/16 fx/32 fx/64 es10 es01 crc21 tmc22 crc20 es00 prm21prm20 prescaler mode register (prm2) capture pulse control register (crc2) 16-bit timer mode control register (tmc2) selector ti22/p62 ti21/p61 ti20/p60 prescaler 1, ?, ?, 1/8 noise rejection circuit noise rejection circuit noise rejection circuit edge detection circuit edge detection circuit dcan 142 chapter 8 16-bit timer 2 user?s manual u15251ee4v0ud00 8.2 16-bit timer 2 configuration timer 2 consists of the following hardware. (1) 16-bit timer register (tm2) tm2 is a 16-bit read-only register that counts count pulses. the counter is incremented in synchronization with the rising edge of an input clock. the count value is reset to 0000h in the following cases: <1> at reset input <2> if tmc22 is cleared (2) capture register 20 (cr20) the valid edge of the ti20/p60 pin can be selected as the capture trigger. setting of the ti20 valid edge is performed by setting of the prescaler mode register (prm2). when the valid edge of the ti20 is detected, an interrupt request (inttm20) is generated. cr20 is read by a 16-bit memo ry manipulation instruction. after reset input, the value of cr20 is undefined. (3) capture register 21 (cr21) the valid edge of the ti21/p61 pin can be selected as the capture trigger. setting of the ti21 valid edge is performed by setting of the prescaler mode register (prm2). when the valid edge of the ti21 is detected, an interrupt request (inttm21) is generated. cr21 is read by a 16-bit memo ry manipulation instruction. after reset input, the value of cr21 is undefined. (4) capture register 22 (cr22) the valid edge of the ti22/p62 pin can be selected as the capture trigger. setting of the ti22 valid edge is performed by setting of the prescaler mode register (prm2). when the valid edge of the ti22 is detected, an interrupt request (inttm22) is generated. cr22 is read by a 16-bit memo ry manipulation instruction. after reset input, the value of cr22 is undefined. table 8-1: timer 2 configuration item configuration timer register 16 bits x 1 (tm2) register capture register: 16 bits x 3 (cr20 to cr22) control register 16 bit timer mode control register (tmc2) capture pulse control register (crc2) prescaler mode register (prm2) 143 chapter 8 16-bit timer 2 user?s manual u15251ee4v0ud00 8.3 16-bit timer 2 control registers the following three types of registers are used to control timer 0. 16-bit timer mode control register (tmc2) capture pulse control register (crc2) prescaler mode register (prm2) (1) 16-bit timer mode control register (tmc2) this register sets the 16-bit timer operating mode and controls the prescaler output signals. tmc0 is set with an 1-bit or an 8-bit memory manipulation instruction. reset input clears tmc2 value to 00h. figure 8-2: 16-bit timer mode control register (tmc2) format cautions: 1. before changing the operation mode, stop the timer operation (by setting 0 to tmc22). 2. bits 0, 1 and bits 3 to 7 must be set to 0. 76543<2>10r/waddress after reset tmc200000tmc2200r/wff65h00h tmc22 timer 2 operating mode selection 0 operation stop (tm2 cleared to 0) 1 operation enabled 144 chapter 8 16-bit timer 2 user?s manual u15251ee4v0ud00 (2) capture pulse control register (crc2) this register specifies the division ratio of the capture pulse input to the 16-bit capture register (cr22) from an external source. crc2 is set with an 8-bit memo ry manipulation instruction. reset input sets crc2 value to 00h. figure 8-3: capture pulse control register (crc2) format cautions: 1. timer operation must be stopped before setting crc2. 2. bits 2 to 7 must be set to 0. 765432<1><0>r/waddress after reset crc2 0 0 0 0 0 0 crc21 crc20 r/w ff67h 00h crc21 crc20 capture pulse selection 0 0 does not divide capture pulse (ti22) 0 1 divides capture pulse by 2 (ti22/2) 1 0 divides capture pulse by 4 (ti22/4) 1 1 divides capture pulse by 8 (ti22/8) 145 chapter 8 16-bit timer 2 user?s manual u15251ee4v0ud00 (3) prescaler mode register (prm2) this register is used to set 16-bit timer (tm2) count clock and valid edge of ti2n (n = 0 to 2) input. prm2 is set with an 8-bit memory manipulation instruction. reset input sets prm2 value to 00h. figure 8-4: prescaler mode register (prm2) format caution: timer operation must be stopped before setting prm2. 76543210r/waddress after reset prm2 es21 es20 es11 es10 es01 es00 prm21 prm20 r/w ff61h 00h es21 es20 selection of valid edge of ti22 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es11 es10 selection of valid edge of ti21 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es01 es00 selection of valid edge of ti20 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges prm21 prm20 selection of count clock 00 f x /2 3 01 f x /2 4 10 f x /2 5 11 f x /2 6 146 chapter 8 16-bit timer 2 user?s manual u15251ee4v0ud00 8.4 16-bit timer 2 operations 8.4.1 pulse width measurement operations it is possible to measure the pulse width of the signals input to the ti20/p60 to ti22/p62 pins by using the 16-bit timer register (tm2). tm2 is used in free-running mode. (1) pulse width measurement with free-running counter and one capture register (ti20) when the edge specified by the prescaler mode regist er (prm2) is input to the ti20/p60 pin, the value of tm2 is taken into 16-bit capture register 20 (cr20) and an external interrupt request sig- nal (inttm20) is set. any of three edge specifications can be selected - rising, falling, or both edges - by means of bits 2 and 3 (es00 and es01) of prm2. for valid edge detection, sampling is performed at the count clock selected by prm2, and a cap- ture operation is only performed when a valid leve l is detected twice, thus eliminating noise with a short pulse width. figure 8-5: configuration diagram for pulse width measurement by using the free running counter fx/2 3 fx/2 4 fx/2 5 fx/2 6 ti20 16-bit timer register (tm2) intovf 16-bit capture register 20 (cr20) internal bus inttm20 selector 147 chapter 8 16-bit timer 2 user?s manual u15251ee4v0ud00 figure 8-6: timing of pulse width measurement operation by using the free running counter and one capture register (with both edges specified) remark: m = 0 to 2 (2) measurement of three pulse widths with the free running counter the 16-bit timer register (tm2) allows simultaneous measurement of the pulse widths of the three signals input to the ti20/p60 to ti22/p62 pins. when the edge specified by bits 2 and 3 (es00 and es01) of prescaler mode register (prm2) is input to the ti20/p60 pin, the value of tm2 is taken into 16-bit capture register 20 (cr20) and an external interrupt request signal (inttm20) is set. also, when the edge specified by bits 4 and 5 (es10 and es11) of prm0 is input to the ti21/p61 pin, the value of tm2 is taken into 16-bit capture register 21 (cr21) and an external interrupt request signal (inttm21) is set. when the edge specified by bits 6 and 7 (es20 and es21) of prm2 is input to the ti22/p62 pin, the value of tm2 is taken into 16-bit capture register 22 (cr22) and external interrupt request sig- nal (inttm22) is set. any of three edge specifications can be selected - rising, falling, or both e dges - as the valid edges for the ti20/p60 to ti22/p62 pins by means of bits 2 and 3 (es00 and es01), bits 4 and 5 (es10 and es11), and bits 6 and 7 (es06 and es07) of prm2, respectively. for ti20/p60 pin valid edge detection, sampling is performed at the interval selected by the pres- caler mode register (prm2), and a capture operation is only performed when a valid level is detected twice, thus eliminates the noise of a short pulse width. t count clock tm2 count value value loaded to cr2m intovf 0000h 0001h d0 d1 ffffh 0000h d2 d3 d3 d2 d1 d0 (d1 ? d0) x t (10000h ? d1 + d2) x t (d3 ? d2) x t ti2m pin input inttm2m 148 chapter 8 16-bit timer 2 user?s manual u15251ee4v0ud00 capture operation capture register operation in capture trigger input is shown. figure 8-7: cr2m capture operation with rising edge specified remark: m = 0 to 2 figure 8-8: timing of pulse width measur ement operation by free running counter (with both edges specified) remark: m = 0 to 2 n = 1, 2 count clock tm2 ti2m rising edge detection cr2m inttm2m n?3 n?2 n?1 n n+1 n count clock tm2 count value ti2m pin input value loaded to cr2m inttm2m ti2n pin input value loaded to cr2n inttm2n intovf (d1 ? d0) x t (10000h ? d0 + d2) x t (10000h ? d1 + (d2 + 1) x t (d3 ? d2) x t t 0000h 0001h d0 d1 ffffh 0000h d2 d3 d3 d1 d0 d1 d2 149 chapter 8 16-bit timer 2 user?s manual u15251ee4v0ud00 8.5 16-bit timer 2 precautions (1) timer start errors an error with a maximum of one clock may occur until counting is started after timer start, because the 16-bit timer register (tm2) is started asynchronously with the count pulse. figure 8-9: 16-bit timer register start timing (2) capture register data retention timings if the valid edge of the ti2m/p6m pin is input during the 16-bit capture register 0m (cr2m) is read, cr2m performs capture operation, but the capture value is not guaranteed. however, the interrupt request flag (inttm2m) is set upon detection of the valid edge. figure 8-10: capture register data retention timing remark: n = 0 to 2 tm2 count value 0000h 0001h 0002h 0004h count pulse timer start 0003h count pulse tm2 count value edge input interrupt request flag capture read signal cr0n interrupt value n-3 n-2 n-1 n n+1 m-3 m-2 m-1 m m+1 m+2 m+3 x n capture operation n 150 chapter 8 16-bit timer 2 user?s manual u15251ee4v0ud00 (3) valid edge setting set the valid edge of the ti2m/p6m pin after setting bit 2 (tmc02) of the 16-bit timer mode control register to 0, and then stopping timer operation. valid edge setting is carried out with bits 2 to 7 (esm0 and esm1) of the prescaler mode register (prm2). remark: m = 0 to 2 (4) occurrence of inttm2n inttm2n occurs even if no capture pulse exists, immediately after the timer operation has been started (tmc02 of tmc2 has been set to 1) with a high level applied to the input pins ti20 to ti22 of 16-bit timer 2. this occurs if the rising edge (with esn1 and esn0 of prm0 set to 0, 1), or both the rising and falling edges (wit h esn1 and esn0 of prm2 set to 1, 1) are selected. inttm2n does not occur if a low level is applied to ti20 to ti22. (5) the value of the timer register when the timer tm2 is disabl ed, the value of the timer register will be undefined. 151 user?s manual u15251ee4v0ud00 chapter 9 8-bit timer/event counters 50 and 51 9.1 8-bit timer/event counters 50 and 51 functions the timer 50 and 51 have the following two modes: mode using tm50 and tm51 alone (individual mode) mode using the cascade connection (16-bit cascade mode connection). (1) mode using tm50 and tm51 alone the timer operate as 8-bit timer/event counters. they have the following functions: interval timer external event counter square-wave output pwm output (2) mode using the cascade connection the timer operates as 16-bit timer/event counter. it has the following functions: interval timer external event counter square-wave output 152 chapter 9 8-bit timer/event counters 50 and 51 user?s manual u15251ee4v0ud00 9.1.1 8-bit operation modes (1) 8-bit interval timer interrupts are generated at the present time intervals. remarks: 1. f x : main system clock oscillation frequency 2. values in parentheses when operated at f x = 8.0 mhz. table 9-1: 8-bit timer/event counter 50 interval times minimum interval width maximum interval width resolution 1/f x (125 ns) 2 8 u 1/f x (32 s) 1/f x (125 ns) 2 1 u 1/f x (250 ns) 2 9 u 1/f x (64 s) 2 1 u 1/f x (250 ns) 2 3 u 1/f x (1 s) 2 11 u 1/f x (256 s) 2 3 u 1/f x (1 s) 2 5 u 1/f x (4 s) 2 13 u 1/f x (1 ms) 2 5 u 1/f x (4 s) 2 7 u 1/f x (16 s) 2 15 u 1/f x (4 ms) 2 7 u 1/f x (16 s) 2 12 u 1/f x (512 s) 2 20 u 1/f x (131 ms) 2 12 u 1/f x (512 s) table 9-2: 8-bit timer/event counter 51 interval times minimum interval width maximum interval width resolution 1/f x (125 ns) 2 8 u 1/f x (32 s) 1/f x (125 ns) 2 1 u 1/f x (250 ns) 2 9 u 1/f x (64 s) 2 1 u 1/f x (250 ns) 2 3 u 1/f x (1 s) 2 11 u 1/f x (256 s) 2 3 u 1/f x (1 s) 2 5 u 1/f x (4 s) 2 13 u 1/f x (1 ms) 2 5 u 1/f x (4 s) 2 8 u 1/f x (32 s) 2 16 u 1/f x (8 ms) 2 8 u 1/f x (32 s) 2 9 u 1/f x (64 s) 2 17 u 1/f x (16 ms) 2 9 u 1/f x (64 s) 153 chapter 9 8-bit timer/event counters 50 and 51 user?s manual u15251ee4v0ud00 (2) external event counter the number of pulses of an externally input signal can be measured. (3) square-wave output a square wave with any selected frequency can be output. remarks: 1. f x : main system clock oscillation frequency 2. values in parentheses when operated at f x = 8.0 mhz. (4) pwm output tm50 and tm51 can generate an 8-bit resolution pwm output. table 9-3: 8-bit timer/event counter 50 square-wave output ranges minimum interval width maximum interval width resolution 1/f x (125 ns) 2 8 u 1/f x (32 s) 1/f x (125 ns) 2 1 u 1/f x (250 ns) 2 9 u 1/f x (64 s) 2 1 u 1/f x (250 ns) 2 3 u 1/f x (1 s) 2 11 u 1/f x (256 s) 2 3 u 1/f x (1 s) 2 5 u 1/f x (4 s) 2 13 u 1/f x (1 ms) 2 5 u 1/f x (4 s) 2 7 u 1/f x (16 s) 2 15 u 1/f x (4 ms) 2 7 u 1/f x (16 s) 2 12 u 1/f x (512 s) 2 20 u 1/f x (131 ms) 2 12 u 1/f x (512 s) table 9-4: 8-bit timer/event counter 51 square-wave output ranges minimum interval width maximum interval width resolution 1/f x (125 ns) 2 8 u 1/f x (32 s) 1/f x (125 ns) 2 1 u 1/f x (250 ns) 2 9 u 1/f x (64 s) 2 1 u 1/f x (250 ns) 2 3 u 1/f x (1 s) 2 11 u 1/f x (256 s) 2 3 u 1/f x (1 s) 2 5 u 1/f x (4 s) 2 13 u 1/f x (1 ms) 2 5 u 1/f x (4 s) 2 8 u 1/f x (32 s) 2 16 u 1/f x (8 ms) 2 8 u 1/f x (32 s) 2 9 u 1/f x (64 s) 2 17 u 1/f x (16 ms) 2 9 u 1/f x (64 s) 154 chapter 9 8-bit timer/event counters 50 and 51 user?s manual u15251ee4v0ud00 9.1.2 16-bit operation modes (1) interval timer interrupts are generated at the present interval time. (2) external event counter the number of pulses of an extern ally input signal can be measured. (3) square-wave output a square wave with any selected frequency can be output. remarks: 1. f x : main system clock oscillation frequency 2. values in parentheses when operated at f x = 8.0 mhz. table 9-5: 16-bit timer/event counter tm50/tm51 interval times minimum interval width maximum interval width resolution 1/f x (125 ns) 2 16 u 1/f x (8 ms) 1/f x (125 ns) 2 1 u 1/f x (250 ns) 2 17 u 1/f x (16 ms) 2 1 u 1/f x (250 ns) 2 3 u 1/f x (1 s) 2 19 u 1/f x (65.5 ms) 2 3 u 1/f x (1 s) 2 5 u 1/f x (4 s) 2 21 u 1/f x (262 ms) 2 5 u 1/f x (4 s) 2 7 u 1/f x (16 s) 2 23 u 1/f x (1.05 s) 2 7 u 1/f x (16 s) 2 12 u 1/f x (512 s) 2 28 u 1/f x (33.6 s) 2 12 u 1/f x (512 s) table 9-6: 16-bit timer/event counter tm50/tm51 square-wave output ranges minimum interval width maximum interval width resolution 1/f x (125 ns) 2 16 u 1/f x (8 ms) 1/f x (125 ns) 2 1 u 1/f x (250 ns) 2 17 u 1/f x (16 ms) 2 1 u 1/f x (250 ns) 2 3 u 1/f x (1 s) 2 19 u 1/f x (65.5 ms) 2 3 u 1/f x (1 s) 2 5 u 1/f x (4 s) 2 21 u 1/f x (262 ms) 2 5 u 1/f x (4 s) 2 7 u 1/f x (16 s) 2 23 u 1/f x (1.05 s) 2 7 u 1/f x (16 s) 2 12 u 1/f x (512 s) 2 28 u 1/f x (33.6 s) 2 12 u 1/f x (512 s) 155 chapter 9 8-bit timer/event counters 50 and 51 user?s manual u15251ee4v0ud00 9.2 8-bit timer/event counters 50 and 51 configurations the 8-bit timer/event counters 50 and 51 consist of the following hardware. figure 9-1: 8-bit timer/event counter 50 block diagram note: refer to figure 9-2 for details of configurations of 8-bit timer/event counters 50 and 51 output control circuits. table 9-7: 8-bit timer/event counters 50 and 51 configurations item configuration timer register 8 bits x 2 (tm50, tm51) register compare register 8 bits x 2 (cr50, cr51) timer output 2 (to50, to51) control register timer clock select register 50 and 51 (tcl50, tcl51) 8-bit timer mode control registers 50 and 51 (tmc50, tmc51) port mode register 2 (pm2) internal bus internal bus ti50 f x f x /2 1 f x /2 3 f x /2 5 f x /2 7 f x /2 12 selector 8-bit compare register 50 (cr50) match 8-bit counter 50 (tm50) 3 selector mask circuit clear ovf tcl502 tcl501 tcl500 timer clock select register 50 (tcl50) timer mode control register 50 (tmc50) tce50 tmc506 tmc504 lvs50 lvr50 tmc501 toe50 s r inv s q r selector inttm50 selector to50 level inversion 156 chapter 9 8-bit timer/event counters 50 and 51 user?s manual u15251ee4v0ud00 figure 9-2: 8-bit timer/event counter 51 block diagram note: refer to figure 9-3 for details of configurations of 8-bit timer/event counters 50 and 51 output control circuits. figure 9-3: block diagram of 8-bit timer/event counters 50 and 51 output control circuit remarks: 1. the section in the broken line is an output control circuit. 2. n = 50, 51 internal bus internal bus ti51 f x f x /2 f x /2 3 f x /2 5 f x /2 8 f x /2 9 selector 8-bit compare register 51 (cr51) match 8-bit counter 51 (tm51) 3 selector mask circuit clear ovf tcl512 tcl511 tcl510 timer clock select register 51 (tcl51) timer mode control register 51 (tmc51) tce51 tmc516 tmc514 lvs51 lvr51 tmc511 toe51 s r inv s q r selector inttm51 selector to51 level inversion reset lvrn lvsn tmcn1 tmcn6 ovfn inttmn tcen inttmn r s q pwm output circuit timer output f/f2 level f/f r s inv q tmcn1 tmcn6 selector p26, p27 output latch pm26, pm27 to50/p26/ti50, to51/p27/ti51 toen 157 chapter 9 8-bit timer/event counters 50 and 51 user?s manual u15251ee4v0ud00 (1) compare register 50 and 51 (cr50, cr51) these 8-bit registers compare the value set to cr50 to 8-bit timer register 5 (tm50) count value, and the value set to cr51 to the 8-bit timer register 51 (tm51) count value, and, if they match, generate interrupts request (inttm 50 and inttm51, respectively). cr50 and cr51 are set with an 8-bit memory manipulation instruction. they cannot be set with a 16-bit memory manipulation instruction. the 00h to ffh values can be set. reset input sets cr50 and cr51 values to 00h. cautions: 1. to use pwm mode, set crn value before setting tmcn (n = 50, 51) to pwm mode. 2. if the data is set in cascade mode, always set it after stopping the timer. (2) 8-bit timer registers 50 and 51 (tm50, tm51) these 8-bit registers count pulses. tm50 and tm51 are read with an 8-bit memory manipulation instruction. reset input sets tm50 and tm51 to 00h. caution: the cascade connection time becomes 00h even when the bit tce50 of the timer tm50 is cleared. 158 chapter 9 8-bit timer/event counters 50 and 51 user?s manual u15251ee4v0ud00 9.3 8-bit timer/event counters 50 and 51 control registers the following three types of registers are used to control the 8-bit timer/event counters 50 and 51. timer clock select register 50 and 51 (tcl50, tcl51) 8-bit timer mode control registers 50 and 51 (tmc50, tmc51) port mode register 2 (pm2) (1) timer clock select register 50 (tcl50) this register sets count clocks of 8-bit timer register 50. tcl50 is set with an 8-bit memory manipulation instruction. reset input sets tcl50 to 00h. figure 9-4: timer clock select register 50 format note: when clock is input from the external, timer output (pwm output) cannot be used. cautions: 1. when rewriting tcl50 to other data, stop the timer operation beforehand. 2. set always bits 3 to 7 to "0". remarks: 1. f x : main system clock oscillation frequency 2. ti50: 8-bit timer register 50 input pin 3. values in parentheses apply to operation with f x = 8.0 mhz 76543210r/waddress after reset tcl50 0 0 0 0 0 tcl502 tcl501 tcl500 r/w ff71h 00h tcl502 tcl501 tcl500 8-bit timer register 50 count clock selection 000 ti50 falling edge note 001 ti50 rising edge note 010 f x (8.0 mhz) 011 f x /2 1 (4.0 mhz) 100 f x /2 3 (1.0 mhz) 101 f x /2 5 (250 khz) 110 f x /2 7 (62.5 khz) 111 f x /2 12 (1.65 khz) other than above setting prohibited 159 chapter 9 8-bit timer/event counters 50 and 51 user?s manual u15251ee4v0ud00 (2) timer clock select register 51 (tcl51) this register sets count clocks of 8-bit timer register 51. tcl51 is set with an 8-bit memory manipulation instruction. reset input sets tcl51 to 00h. figure 9-5: timer clock select register 51 format note: when clock is input from the external, timer output (pwm output) cannot be used. cautions: 1. when rewriting tcl51 to other data, stop the timer operation beforehand. 2. set always bits 3 to 7 to "0". remarks: 1. f x : main system clock oscillation frequency 2. ti51: 8-bit timer register 51 input pin 3. values in parentheses apply to operation with f x = 8.0 mhz 76543210r/waddress after reset tcl51 0 0 0 0 0 tcl512 tcl511 tcl510 r/w ff75h 00h tcl512 tcl511 tcl510 8-bit timer register 51 count clock selection 000 ti51 falling edge note 001 ti51 rising edge note 010 f x (8.0 mhz) 011 f x /2 1 (4.0 mhz) 100 f x /2 3 (1.0 mhz) 101 f x /2 5 (250 khz) 110 f x /2 8 (31.25 khz) 111 f x /2 9 (15.6 khz) other than above setting prohibited 160 chapter 9 8-bit timer/event counters 50 and 51 user?s manual u15251ee4v0ud00 (3) 8-bit timer mode cont rol register 50 (tmc50) this register enables/stops operation of 8-bit timer register 50, sets the operating mode of 8-bit timer register 50 and controls operation of 8-bit timer/event counter 50 output control circuit. it selects the r-s flip-flop (timer output f/f 1, 2) setting/resetting, the active level in pwm mode, inversion enabling/disabling in modes other than pwm mode and 8-bit timer/event counter 5 timer output enabling/disabling. tmc50 is set with an 1-bit or an 8-bit memory manipulation instruction. reset input sets tmc50 to 00h. figure 9-6: 8-bit timer mode control register 50 format cautions: 1. timer operation must be stopped before setting tmc50. 2. if lvs50 and lvr50 are read after data are set, they will be 0. 3. be sure to set bit 4 and bit 5 to 0. <7> 6 5 4 <3> <2> 1 <0> r/w address after reset tmc50 tce50 tmc506 0 0 lvs50 lvr50 tmc501 toe50 r/w ff70h 00h toe50 8-bit timer/event co unter 50 output control 0 output disabled (port mode) 1 output enabled tmc501 in pwm mode in other mode active level selection timer output f/f1 control 0 active high inversion operation disabled 1 active low inversion operation enabled lvs50 lvr50 8-bit timer/event counter 50 timer output f/f1 status setting 0 0 no change 0 1 timer output f/f1 reset (0) 1 0 timer output f/f1 set (1) 1 1 setting prohibited tmc506 8-bit timer/event counter 50 operating mode selection 0 clear & start mode on match of tm50 and cr50 1 pwm mode (free-running) tce50 8-bit timer register 50 operation control 0 operation stop (tm50 clear to 0) 1 operation enable 161 chapter 9 8-bit timer/event counters 50 and 51 user?s manual u15251ee4v0ud00 (4) 8-bit timer mode control register 51 (tmc51) this register enables/stops operation of 8-bit timer register 51, sets the operating mode of 8-bit timer register 51 and controls operation of 8-bit timer/event counter 51 output control circuit. it selects the r-s flip-flop (timer output f/f 1, 2) setting/resetting, active level in pwm mode, inver- sion enabling/disabling in modes other than pwm mode and 8-bit timer/event counter 51 timer output enabling/disabling. tmc51 is set with an 1-bit or an 8-bit memory manipulation instruction. reset input sets tmc51 to 00h. figure 9-7: 8-bit timer mode control register 51 format (1/2) <7> 6 5 4 <3> <2> 1 <0> r/w address after reset tmc51 tce51 tmc516 0 tmc514 lvs51 lvr51 tmc511 toe51 r/w ff74h 00h toe51 8-bit timer/event counter 51 output control 0 output disabled (port mode) 1 output enabled tmc511 in pwm mode in other mode active level selection timer output f/f1 control 0 active high inversion operation disabled 1 active low inversion operation enabled lvs51 lvr50 8-bit timer/event counter 51 timer output f/f1 status setting 0 0 no change 0 1 timer output f/f1 reset (0) 1 0 timer output f/f1 set (1) 1 1 setting prohibited tmc514 individual of cascade mode connection 0 individual mode (8-bit timer/counter mode) 1 cascade connection mode (16-bit timer/counter mode) 162 chapter 9 8-bit timer/event counters 50 and 51 user?s manual u15251ee4v0ud00 figure 9-7: 8-bit timer mode control register 51 format (2/2) cautions: 1. timer operation must be stopped before setting tmc51. 2. if lvs51 and lvr51 are read after data are set, they will be 0. 3. be sure to set bit 5 to 0. (5) port mode register 2 (pm2) this register sets port 2 input/output in 1-bit units. when using the p26/ti50/to50 and p27/ti51/to51 pins for timer output, set pm26, pm27 and the output latches of p26 and p27 to 0. pm2 is set with an 1-bit or an 8-bit memory manipulation instruction. reset input sets pm2 to ffh. figure 9-8: port mode register 2 format tmc516 8-bit timer/event counter 51 operating mode selection 0 clear & start mode on match of tm51 and cr51 1 pwm mode (free-running) tce51 8-bit timer register 51 operation control 0 operation stop (tm51 clear to 0) 1 operation enable 76543210r/waddress after reset pm2 pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 r/w ff22h ffh pm2n pm2n input/output mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) 163 chapter 9 8-bit timer/event counters 50 and 51 user?s manual u15251ee4v0ud00 9.4 8-bit timer/event counters 50 and 51 operations 9.4.1 interval timer operations (8 -bit timer/event counter mode) setting the 8-bit timer mode control registers (tmc50 and tmc51) as shown in figure 9-9 allows oper- ation as an interval timer. interrupts are generated repeatedly using the count value preset in 8-bit com- pare registers (cr50 and cr51) as the interval. when the count value of the 8-bit timer register 50 or 51 (tm50, tm51) matches the value set to cr50 or cr51, counting continues with the tm50 or tm51 value cleared to 0 and the interrupt request signal (inttm50, inttm51) is generated. count clock of the 8-bit timer register 50 (tm50) c an be selected with the timer clock select register 50 (tcl50) and count clock of the 8 bit timer register 51 (tm51) can be selected with the timer clock select register 51 (tcl51). figure 9-9: 8-bit timer mode control register settings for interval timer operation setting method (1) set each register tcl5n : selects the count clock cr5n : compare value tmc5n : selects the clear and start mode when tm5n and cr5n match. (tmc5n = 0000xxxx0b, x is not done care). (2) when tce5n = 1 is set, counting starts. (3) when the values of tm5n and cr5n match, inttm5n is generated (tm5n is cleared to 00h). (4) then, inttm5n is repeatedly generated during the same interval. when counting stops, set tce5n = 0. remarks: 1. 0/1: setting 0 or 1 allows another function to be used simultaneously with the interval timer. see 9.3 (3)?8-bit timer mode control register 50 (tmc50)? on page 160 and (4)?8- bit timer mode control register 51 (tmc51)? on page 161 for details. 2. n = 50, 51 3. tmc5n4 is only available at tm51. 1 tcen 0 tmcn6 0 0 0/1 lvsn lvrn tmcn1 toen tmcn 0/1 0/1 0/1 clear and start on match of tmn and crn tmn operation enable tmcn4 8-bit timer/event counter mode 164 chapter 9 8-bit timer/event counters 50 and 51 user?s manual u15251ee4v0ud00 figure 9-10: interval timer operation timings (1/3) (a) when n = 00h to ffh remarks: 1. interval time = (n + 1) x t: n = 00h to ffh 2. n = 50, 51 (b) when crn = 00h remark: n = 50, 51 t 00 01 n 00 01 n 00 01 n n n n n clear clear count start interrupt acknowledge interrupt acknowledge interval time interval time interval time count clock tmn count value crn tcen inttmn ton t count clock tmn crn tcen inttmn tion interval time 00h 00h 00h 00h 00h 165 chapter 9 8-bit timer/event counters 50 and 51 user?s manual u15251ee4v0ud00 figure 9-10: interval timer operation timings (2/3) (c) when crn = ffh remark: n = 50, 51 (d) operated by cr5n transition (m < n) remark: n = 50, 51 t count clock tmn crn tcen inttmn tion 01 fe ff 00 fe ff 00 ff ff ff interval time interrupt received interrupt received count clock tmn crn tcen inttmn tion 00h n n m n ffh 00h m 00h m crn transition tmn overflows since m < n 166 chapter 9 8-bit timer/event counters 50 and 51 user?s manual u15251ee4v0ud00 figure 9-10: interval timer operation timings (3/3) (e) operated by cr5n transition (m > n) remark: n = 50, 51 count clock tmn crn tcen inttmn tion n n 00h 01h n 1 m 00h 01h m crn transition 167 chapter 9 8-bit timer/event counters 50 and 51 user?s manual u15251ee4v0ud00 remarks: 1. f x : main system clock oscillation frequency 2. values in parentheses apply to operation with f x = 8.0 mhz. table 9-8: 8-bit timer/event counters 50 interval times tcln2 tcln1 tcln0 minimum interval time maximum interval time resolution 0 0 0 t/n input cycle 2 8 u t/n input cycle t/n input edge input cycle 0 0 1 t/n input cycle 2 8 u t/n input cycle t/n input edge input cycle 010 1/f x (125 n s ) 2 8 u 1/f x (32 s) 1/f x (125 n s ) 011 2 1 u 1/f x ((250 n s )2 9 u 1/f x (64 ms) 2 1 u 1/f x ((250 n s ) 100 2 3 u 1/f x (1 s) 2 11 u 1/f x (256 ms) 2 3 u 1/f x (1 s) 101 2 5 u 1/f x (4 s) 2 13 u 1/f x (1 ms) 2 5 u 1/f x (4 s) 110 2 7 u 1/f x (16 s) 2 15 u 1/f x (4 ms) 2 7 u 1/f x (16 s) 111 2 12 u 1/f x (512 s) 2 20 u 1/f x (131 ms) 2 12 u 1/f x (512 s) other than above setting prohibited table 9-9: 8-bit timer/event counters 51 interval times tcln2 tcln1 tcln0 minimum interval time maximum interval time resolution 0 0 0 t/n input cycle 2 8 u t/n input cycle t/n input edge input cycle 0 0 1 t/n input cycle 2 8 u t/n input cycle t/n input edge input cycle 010 1/f x (125 n s ) 2 8 u 1/f x (32 s) 1/f x (125 n s ) 011 2 1 u 1/f x ((250 n s )2 9 u 1/f x (64 ms) 2 1 u 1/f x ((250 n s ) 100 2 3 u 1/f x (1 s) 2 11 u 1/f x (256 ms) 2 3 u 1/f x (1 s) 101 2 5 u 1/f x (4 s) 2 13 u 1/f x (1 ms) 2 5 u 1/f x (4 s) 110 2 8 u 1/f x (32 s) 2 16 u 1/f x (8 ms) 2 8 u 1/f x (32 s) 111 2 9 u 1/f x (64 s) 2 17 u 1/f x (16 ms) 2 9 u 1/f x (64 s) other than above setting prohibited 168 chapter 9 8-bit timer/event counters 50 and 51 user?s manual u15251ee4v0ud00 9.4.2 external event counter operation the external event counter counts the number of external clock pulses to be input to the ti50/p26/to50 and ti51/p27/to51 pins with 8-bit timer registers 50 and 51 (tm50 and tm51). tm50 and tm51 are incremented each time the valid edge specified with timer clock select registers 50 and 51 (tcl50 and tcl51) is input. either rising or falling edge can be selected. when the tm50 and tm51 counted values match the values of 8-bit compare registers (cr50 and cr51), tm50 and tm51 are cleared to 0 and the interrupt request signals (inttm50 and inttm51) are generated. figure 9-11: 8-bit timer mode control register setting for external event counter operation remarks: 1. n = 50, 51 2. x: don?t care figure 9-12: external event counter operation timings (with rising edge specified) remarks: 1. n = 00h to ffh 2. n = 50, 51 3. the bit tmcn4 is just valid for timer tm51. 1 tcen 0 tmcn6 00 x lvsn lvrn tmcn1 toen tmcn x x 0 clear and start mode on match of tmn and crn tmn operation enable tmcn4 8-bit timer/event counter mode ton output disable 00 01 13 n count clock tmn count value crn tcen inttmn 05 n-1 00 02 03 01 02 04 n 169 chapter 9 8-bit timer/event counters 50 and 51 user?s manual u15251ee4v0ud00 9.4.3 square-wave output a square wave with any selected frequency is output at intervals of the value preset to 8-bit compare registers (cr50 and cr51). the to50/p26/ti50 or to51/p27/ti51 pin output status is reversed at intervals of the count value pre- set to cr50 or cr51 by setting bit 1 (tmc501) and bit 0 (toe50) of the 8-bit timer output control regis- ter 5 (tmc50), or bit 1 (tmc511) and bit 0 (toe51) of the 8-bit timer mode control register 6 (tmc51) to 1. this enables a square wave of a selected frequency to be output. figure 9-13: 8-bit timer mode control register settings for square-wave output operation setting method (1) set the registers set the port latch and port mode register to 0. tcl5n : selects the count clock cr5n : compare value tmc5n : selects the clear and start mode when tm5n and cr5n match. inversion of timer output flip-flop enabled timer output enabled o toe5n = 1 (2) when tce5n = 1 is set, the counter starts operating. (3) when the values of tm5n and cr5n match, the timer output flip-flop inverts. also, inttm5n is generated and tm5n is cleared to 00h. (4) then, the timer output flip-flop is inverted for the same interval to output a square wave from to5n. caution: when ti50/p26/to50 or ti51/p27/to51 pi n is used as the timer output, set port mode register (pm26 or pm27), and output latch to 0. remarks: 1. n = 50, 51 2. the bit tmc5n4 is just valid for timer tm51. lvs5n lvr5n setting state of timer output flip-flop 1 0 high level output 0 1 low level output 1 tcen 0 tmcn6 tmcn4 0 0 0/1 lvsn lvrn tmcn1 toen tmcn 0/1 1 1 ton output enable inversion of output on match of tmn and crn specifies to1 output f/f1 initial value clear and start mode on match of tmn and crn tmn operation enable tmn operation enable 170 chapter 9 8-bit timer/event counters 50 and 51 user?s manual u15251ee4v0ud00 figure 9-14: square-wave output operation timing note: ton output initial value can be set by bits 2 and 3 (lvrn, lvsn) of the 8-bit timer mode control register tcmn. remark: n = 50, 51 remarks: 1. f x : main system clock oscillation frequency 2. values in parentheses when operated at f x = 8.0 mhz. table 9-10: 8-bit timer/event counters 50 square-wave output ranges (8-bit timer/event counter mode) tcl502 tcl501 tcl500 minimum pulse time maximum pulse time resolution 010 1/f x (125 n s ) 2 8 u 1/f x (32 s) 1/f x (125 n s ) 011 2 1 u 1/f x ((250 n s )2 9 u 1/f x (64 ms) 2 1 u 1/f x ((250 n s ) 100 2 3 u 1/f x (1 s) 2 11 u 1/f x (256 ms) 2 3 u 1/f x (1 s) 101 2 5 u 1/f x (4 s) 2 13 u 1/f x (1 ms) 2 5 u 1/f x (4 s) 110 2 7 u 1/f x (16 s) 2 15 u 1/f x (4 ms) 2 7 u 1/f x (16 s) 111 2 12 u 1/f x (512 s) 2 20 u 1/f x (131 ms) 2 12 u 1/f x (512 s) table 9-11: 8-bit timer/event counters 51 square-wave output ranges (8-bit timer/event counter mode) tcl502 tcl501 tcl500 minimum pulse time maximum pulse time resolution 010 1/f x (125 n s ) 2 8 u 1/f x (32 s) 1/f x (125 n s ) 011 2 1 u 1/f x ((250 n s )2 9 u 1/f x (64 ms) 2 1 u 1/f x ((250 n s ) 100 2 3 u 1/f x (1 s) 2 11 u 1/f x (256 ms) 2 3 u 1/f x (1 s) 101 2 5 u 1/f x (4 s) 2 13 u 1/f x (1 ms) 2 5 u 1/f x (4 s) 110 2 8 u 1/f x (32 s) 2 16 u 1/f x (8 ms) 2 8 u 1/f x (32 s) 111 2 9 u 1/f x (64 s) 2 17 u 1/f x (16 ms) 2 9 u 1/f x (64 s) count clock tmn count value crn t0n note count start 00h 01h n-1 n 02h 00h n 02h 00h 01h n-1 n 171 chapter 9 8-bit timer/event counters 50 and 51 user?s manual u15251ee4v0ud00 9.4.4 pwm output operations setting the 8-bit timer mode control registers (tmc50 and tmc51) as shown in figure 9-15 allows operation as pwm output. pulses with the duty rate determined by the values preset in 8-bit compare registers (cr50 and cr51) output from the to50/p26/ti50 or to51/p27/ti51 pin. select the active level of pwm pulse with bit 1 of the 8-bit timer mode control register 50 (tmc50) or bit 1 of the 8-bit timer mode control register 51 (tmc51). this pwm pulse has an 8-bit resolution. the pulse can be converted into an analog voltage by integrat- ing it with an external low-pass filter (lpf). count clock of the 8-bit timer register 50 (tm50) can be selected with the timer clock select register 50 (tcl50) and count clock of the 8-bit timer register 51 (tm51) can be selected with the timer clock select register 51 (tcl51). pwm output enable/disable can be selected with bit 0 (toe50) of tmc50 or bit 0 (toe51) of tmc51. figure 9-15: 8-bit timer control register settings for pwm output operation setting method (1) set the port latch and port mode register to "0". (2) set the active level width in the 8-bit compare register n (cr5n). (3) select the count clock in the timer clock selection register n (tcl5n). (4) set the active level in bit 1 (tmc5n1) of tmc5n. (5) if bit 7 (tce5n) of tmc5n is set to "1", counting starts. when counting starts, set tce5n to "0". remarks: 1. n = 50, 51 2. x: don?t care pwm output operation (1) when counting starts, the pwm output (output from to5n) outputs the inactive level until an overflow occurs. (2) when the overflow occurs, the active level specified in step (1) in the setting method is output. the active level is output until cr5n and the count of the 8-bit counter n (tm5n) match. (3) the pwm output after cr5n and the count match is the inactive level until an overflow occurs again. (4) steps (2) and (3) repeat until counting stops. (5) if counting is stopped by tce5n = 0, the pwm output goes to the inactive level. remark: n = 50, 51 1 tcen 1 tmcn6 tmcn4 00x lvsn lvrn tmcn1 toen tmcn x 0/1 1 ton output enable sets active level pwm mode tmn operation enable 8-bit timer/event counter mode 172 chapter 9 8-bit timer/event counters 50 and 51 user?s manual u15251ee4v0ud00 figure 9-16: pwm output operati on timing (active high setting) remark: n = 50, 51 figure 9-17: pwm output operation timing s (crn0 = 00h, active high setting) remark: n = 50, 51 count clock tmn count value crn tcen inttmn ton 01 02 ff 00 01 02 n n+1 n+2 n+3 00 ovfn mn n 00 inactive level crn changing active level inactive level inactive level (m n) count clock tmn count value crn tcen inttmn ton 01 02 ff 00 01 02 ff 00 01 02 00 ovfn m00 00 00 inactive level crn changing (m 00) inactive level 173 chapter 9 8-bit timer/event counters 50 and 51 user?s manual u15251ee4v0ud00 figure 9-18: pwm output operation timings (crn = ffh, active high setting) remark: n = 50, 51 figure 9-19: pwm output operation timings (crn changing, active high setting) remark: n = 50, 51 caution: if crn is changed during tmn operation, the value changed is not reflected until tmn overflows. count clock tmn count value crn tcen inttmn ton 01 02 ff 00 01 02 ff 00 01 02 00 ovfn ff ff ff 00 inactive level inactive level active level inactive level active level count clock tmn count value crn0 tcen inttmn ton ovfn active level inactive level 00 ff n+2 n+1 n 02 01 00 ff 01 02 m+2 m+1 m m+3 00 active level inactive level crn changing n n mm (n m) 174 chapter 9 8-bit timer/event counters 50 and 51 user?s manual u15251ee4v0ud00 9.5 operation as interval timer (16-bit operation) (1) cascade (16-bit timer) mode (tm50 and tm51) the 16-bit resolution timer/counter mode is set by setting bit 4 (tmc514) of the 8-bit timer mode control register 51 (tmc51) to ?1?. in this mode, tm50 and tm51 operate as a 16-bit interval timer that repeatedly generates an inter- rupt request at intervals specified by the count value set in advance to 8-bit compare registers 50 and 51 (cr50 and cr51). figure 9-20: 8-bit timer mode control register settings for 16-bit interval timer operation remark: 0/1: setting 0 or 1 allows another function to be used simultaneously with the interval timer. 1 tce50 0 tmc506 0 0 0/1 lvs50 lvr50 tmc501 toe50 tmc50 0/1 0/1 0 clear and start on match of tm50/tm51 and cr50/cr51 tm50 operation enable 1 tce51 0 tmc516 0 1 0/1 lvs51 lvr51 tmc511 toe51 tmc51 0/1 0/1 0 clear and start on match of tm50/tm51 and cr50/cr51 tm51 operation enable tmc514 16-bit timer/counter mode 175 chapter 9 8-bit timer/event counters 50 and 51 user?s manual u15251ee4v0ud00 176 chapter 9 8-bit timer/event counters 50 and 51 user?s manual u15251ee4v0ud00 figure 9-21 shows an example of timing in the 16-bit resolution cascade mode. figure 9-21: 16-bit resolution cascade mode (with tm50 and tm51) enables operation counting starts count clock tm50 tm51 tce51 to50 01h n n+1 00h 00h tce50 ffh 01h ffh 00h 00h n 00h 01h ffh cr50 cr51 m n inttm50 01h 02h m-1 m 00h a 00h b 00h interrupt request generated level inverted counter cleared operation stops interval time 00h 177 chapter 9 8-bit timer/event counters 50 and 51 user?s manual u15251ee4v0ud00 caution: the clock selection in the cascade mode (16-bit timer/event counter mode) is done by the register tcl50. remarks: 1. f x : main system clock oscillation frequency. 2. values in parentheses when operated at f x = 8.0 mhz. table 9-12: 8-bit timer/event counters interv al times (16-bit timer/event counter mode) tcl502 tcl501 tcl500 minimum interval time maximum interval time resolution 0 0 0 ti50 input cycle 2 16 u tin input cycle tin input cycle 0 0 1 ti50 input cycle 2 16 u tin input cycle tin input cycle 010 1/f x (125 n s ) 2 16 u 1/f x (8 ms) 1/f x (125 n s ) 011 2 1 u 1/f x ((250 n s )2 17 u 1/f x (16 ms) 2 1 u 1/f x ((250 n s ) 100 2 3 u 1/f x (1 s) 2 19 u 1/f x (65.5 ms) 2 3 u 1/f x (1 s) 101 2 5 u 1/f x (4 s) 2 21 u 1/f x (262 ms) 2 5 u 1/f x (4 s) 110 2 7 u 1/f x (16 s) 2 23 u 1/f x (1.05 s) 2 7 u 1/f x (16 s) 111 2 12 u 1/f x (512 s) 2 28 u 1/f x (33.6 s) 2 12 u 1/f x (512 s) table 9-13: 8-bit timer/event counter square-wave output ranges (16-bit timer/event counter mode) tcl502 tcl501 tcl500 minimum pulse width maximum pulse width resolution 010 1/f x (125 n s ) 2 16 u 1/f x (8 ms) 1/f x (125 n s ) 011 2 1 u 1/f x ((250 n s )2 17 u 1/f x (16 ms) 2 1 u 1/f x ((250 n s ) 100 2 3 u 1/f x (1 s) 2 19 u 1/f x (65.5 ms) 2 3 u 1/f x (1 s) 101 2 5 u 1/f x (4 s) 2 21 u 1/f x (262 ms) 2 5 u 1/f x (4 s) 110 2 7 u 1/f x (16 s) 2 23 u 1/f x (1.05 s) 2 7 u 1/f x (16 s) 111 2 12 u 1/f x (512 s) 2 28 u 1/f x (33.6 s) 2 12 u 1/f x (512 s) 178 chapter 9 8-bit timer/event counters 50 and 51 user?s manual u15251ee4v0ud00 9.6 cautions on 8-bit timer/event counters 50 and 51 (1) timer start errors an error with a maximum of one clock might occur concerning the time required for a match signal to be generated after the timer starts. this is because 8-bit timer registers 50 and 51 are started asynchronously with the count pulse. figure 9-22: 8-bit timer registers 50 and 51 start timings remark: n = 50, 51 (2) compare registers 50 and 51 sets the 8-bit compare registers (cr50 and cr51) can be set to 00h. thus, when an 8-bit compare register is used as an event counter, one-pulse count operation can be carried out. figure 9-23: external event counter operation timings remark: n = 50, 51 count pulse tmn count value 00h timer start 01h 02h 03h 04h tin input crn 00h tmn count value 00h 00h 00h 00h ton interrupt request flag 179 chapter 9 8-bit timer/event counters 50 and 51 user?s manual u15251ee4v0ud00 (3) operation after compare register ch ange during timer count operation if the values after the 8-bit compare registers (cr50 and cr51) are changed are smaller than those of 8-bit timer registers (tm50 and tm51), tm50 and tm51 continue counting, overflow and then restarts counting from 0. thus, if the value (m) after cr50 and cr51 change is smaller than that (n) before change it is necessary to restart the timer after changing cr50 and cr51. figure 9-24: timings after compare register change during timer count operation remark: n = 50, 51 count pulse crn n x x-1 ffffh 0000h 0001h m 0002h tmn count value 180 user?s manual u15251ee4v0ud00 [memo] 181 user?s manual u15251ee4v0ud00 chapter 10 watch timer 10.1 watch timer functions the watch timer has the following functions: watch timer interval timer the watch timer and the interval timer can be used simultaneously. the figure 10-1 shows watch timer block diagram. figure 10-1: block diagram of watch timer f x /2 8 f xt f w f w 2 4 f w 2 5 f w 2 6 f w 2 7 f w 2 8 f w 2 9 clear 9-bit prescaler clear 5-bit counter intwt intwti wtm7 wtm6 wtm5 wtm4 wtm2 wtm1 wtm0 watch timer mode control register (wtm) internal bus selector selector wtm3 selector selector 3 182 chapter 10 watch timer user?s manual u15251ee4v0ud00 (1) watch timer when the main system clock or subsystem clock is used, interrupt requests (intwt) are generated at the following time intervals. remarks: 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. f w : watch timer clock frequency (2) interval timer interrupt requests (intwti) are generated at the preset time interval. remarks: 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. f w : watch timer clock frequency table 10-1: watch timer interval time watch timer interval time f w = f x /2 8 f w = f xt when operated at f x = 8.00 mhz when operated at f x = 5.00 mhz when operated at f xt = 32.768 khz 2 5 /f w 1.02 ms 1.64 ms 976.56 s 2 9 /f w 16.38 ms 26.21 ms 15.63 ms 2 10 /f w 32.77 ms 52.43 ms 31.25 ms 2 11 /f w 65.54 ms 104.86 ms 62.5 ms 2 12 /f w 131.07 ms 209.72 ms 125 ms 2 13 /f w 262.14 ms 419.43 ms 250 ms 2 14 /f w 524.29 ms 838.86 ms 500 ms table 10-2: interval timer interval time interval time f w = f x /2 8 f w = f xt when operated at f x = 8.00 mhz when operated at f x = 5.00 mhz when operated at f xt = 32.768 khz 2 4 /f w 512 s 819 s 488 s 2 5 /f w 1 ms 1.6 ms 977 s 2 6 /f w 2 ms 3.2 ms 1.95 ms 2 7 /f w 4 ms 6.55 ms 3.91 ms 2 8 /f w 8.19 ms 13.1 ms 7.81 ms 2 9 /f w 16.38 ms 26.2 ms 15.6 ms 183 chapter 10 watch timer user?s manual u15251ee4v0ud00 10.2 watch timer configuration the watch timer consists of the following hardware. table 10-3: watch timer configuration item configuration counter 5 bits u 1 prescaler 9 bits u 1 control register watch timer m ode control register (wtm) 184 chapter 10 watch timer user?s manual u15251ee4v0ud00 10.3 watch timer mode register (wtm) this register sets the watch timer count clock, the watch timer operating mode, and prescaler interval time and enables/disables prescaler and 5-bit counter operations. wtm is set with an 1-bit or an 8-bit memory manipulation instruction. reset input sets wtm to 00h. figure 10-2: watch timer mode control register (wtm) format (1/2) 76543210r/waddress after reset wtmwtm7wtm6wtm5wtm4wtm3wtm2wtm1wtm0r/wff41h 00h wtm7 watch timer count clock selection 0 input clock set to f x / 2 8 1 input clock set to f xt wtm6 wtm5 wtm4 prescaler interval time selection f x = 8.00 mhz operation f x = 5.00 mhz operation f xt = 32.768 khz operation 000 2 4 /f w (512 s) 2 4 /f w (819 s) 2 4 /f w (488 s) 001 2 5 /f w (1 ms) 2 5 /f w (1.6 ms) 2 5 /f w (977 s) 010 2 6 /f w (2 ms) 2 6 /f w (3.2 ms) 2 6 /f w (1.95 ms) 011 2 7 /f w (4 ms) 2 7 /f w (6.55 ms) 2 7 /f w (3.91 ms) 100 2 8 /f w (8.19 ms) 2 8 /f w (13.1 ms) 2 8 /f w (7.81 ms) 101 2 9 /f w (16.38 ms) 2 9 /f w (26.2 ms) 2 9 /f w (15.6 ms) other than above s etting prohibited wtm3 watch operati ng mode selections 0 normal operating mode (interrupt generation at 2 14 /f w ) 1 fast feed operating mode (interrupt generation at 2 5 /f w ) wtm2 interrupt generation mode select for normal operating mode 0 standard mode (interrupt generation fixed at 2 14 /f w ) 1 selectable mode (interrupt generation at 2 9 /f w to 2 14 /f w ) 185 chapter 10 watch timer user?s manual u15251ee4v0ud00 figure 10-2: watch timer mode control register (wtm) format (2/2) caution: when the watch timer is used, the prescaler should not be cleared frequently. when rewriting wtm4 to wtm6 to other data, stop the timer operation beforehand. remarks: 1. f w : watch timer clock frequency (f x /2 8 or f xt ) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency wtm1 5-bit counter operation control 0 clear after operation stop 1 operation enable wtm0 prescaler operation control 0 clear after operation stop 1 operation enable 186 chapter 10 watch timer user?s manual u15251ee4v0ud00 10.4 watch timer operations 10.4.1 watch timer operation the watch timer operates as internal timer and generates interrupt requests repeatedly at a defined interval. when the 32.768 khz subsystem clock is used, the watch timer generates also 0.25 -second and 0.5-second intervals which can be used for clocks etc. the interval time can be selected with the bits 2, 3, 4 to 6 and 7 of the watch timer mode control regis- ter. remarks: 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. f w : watch timer clock frequency 4. x : don't care table 10-4: watch timer operation wtm6 wtm5 wtm4 wtm3 wtm2 interval time f w = f x /2 8 f w = f xt f x = 8.00 mhz operation f x = 5.00 mhz operation f xt = 32.768 mhz operation xxx1x 2 5 /f w 1 ms 1.63 ms 976.56 ms 00001 2 9 /f w 16.38 ms 26.21 ms 15.62 ms 00101 2 10 /f w 32.76 ms 52.42 ms 31.25 ms 01001 2 11 /f w 65.54 ms 104.85 ms 62.5 ms 01101 2 12 /f w 131.07 ms 209.71 ms 125 ms 10001 2 13 /f w 262.14 ms 413.43 ms 250 ms 1010x 2 14 /f w 524.29 ms 838.86 ms 500 ms other than above setting prohibited 187 chapter 10 watch timer user?s manual u15251ee4v0ud00 10.4.2 interval timer operation the watch timer operates as interval timer which generates interrupt request repeatedly at an interval of the preset count value. the interval time can be selected with bits 4 to 6 (wtm4 to wtm6) of the watch timer mode control register (wtm). remarks: 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. f w : watch timer clock frequency table 10-5: interval timer operation wtm6 wtm5 wtm4 interval time f w = f x /2 8 f w = f xt f x = 8.00 mhz operation f x = 5.00 mhz operation f xt = 32.768 mhz operation 000 2 4 u 1/f w 512 s 819 s 488 s 001 2 5 u 1/f w 1 ms 1.6 ms 977 s 010 2 6 u 1/f w 2 ms 3.2 ms 1.95 ms 011 2 7 u 1/f w 4 ms 6.55 ms 3.91 ms 100 2 8 u 1/f w 8.19 ms 13.1 ms 7.81 ms 101 2 9 u 1/f w 16.38 ms 26.2 ms 15.6 ms other than above setting prohibited 188 chapter 10 watch timer user?s manual u15251ee4v0ud00 figure 10-3: operation timing of watch timer/interval timer remark: f w : watch timer clock frequency 0h start overflow overflow 5-bit counter count clock f w watch timer interrupt intwt interval timer interrupt intwti interrupt time of watch timer interval timer (t) t interrupt time of watch timer 189 user?s manual u15251ee4v0ud00 chapter 11 watchdog timer 11.1 watchdog timer functions the watchdog timer has the following functions: watchdog timer interval timer caution: select the watchdog timer mode or the interval timer mode with the watchdog timer mode register (wdtm). (1) watchdog timer mode an inadvertent program loop is detected.upon detection of the inadvertent program loop, a non-maskable interr upt request or reset can be generated. remark: figures in parentheses apply to operation with f x = 8.0 mhz. table 11-1: watchdog timer inadverten t program overrun detection times runaway detection time 2 12 u 1/f x 2 12 u 1/f x (512 s) 2 13 u 1/f x 2 13 u 1/f x (1 ms) 2 14 u 1/f x 2 14 u 1/f x (2 ms) 2 15 u 1/f x 2 15 u 1/f x (4 ms) 2 16 u 1/f x 2 16 u 1/f x (8.19 ms) 2 17 u 1/f x 2 17 u 1/f x (16.38 ms) 2 18 u 1/f x 2 18 u 1/f x (32.76 ms) 2 20 u 1/f x 2 20 u 1/f x (131 ms) 190 chapter 11 watchdog timer user?s manual u15251ee4v0ud00 (2) interval timer mode interrupts are generated at the preset time intervals. remark: figures in parentheses apply to operation with f x = 8.0 mhz. table 11-2: interval times interval time 2 12 u 1/f x 2 12 u 1/f x (512 s) 2 13 u 1/f x 2 13 u 1/f x (1 ms) 2 14 u 1/f x 2 14 u 1/f x (2 ms) 2 15 u 1/f x 2 15 u 1/f x (4 ms) 2 16 u 1/f x 2 16 u 1/f x (8.19 ms) 2 17 u 1/f x 2 17 u 1/f x (16.38 ms) 2 18 u 1/f x 2 18 u 1/f x (32.76 ms) 2 20 u 1/f x 2 20 u 1/f x (131 ms) 191 chapter 11 watchdog timer user?s manual u15251ee4v0ud00 11.2 watchdog timer configuration the watchdog timer consists of the following hardware. figure 11-1: watchdog timer block diagram table 11-3: watchdog timer configuration item configuration control register timer clock select register (wdcs) watchdog timer mode register (wdtm) prescaler f x 2 4 f x 2 5 f x 2 6 f x 2 7 f x 2 8 f x 2 9 selector watchdog timer mode register internal bus internal bus wdcs2 wdcs1 wdcs0 f x /2 8 f x 2 10 watchdog timer clock selection register 3 wdtm4 wdtm3 8-bit counter tmmk4 run tmif4 intwdt maskable interrupt request reset intwdt non-maskable interrupt request control circuit f x 2 12 192 chapter 11 watchdog timer user?s manual u15251ee4v0ud00 11.3 watchdog timer control registers the following two types of registers are used to control the watchdog timer. watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm) (1) watchdog timer clock select register (wdcs) this register sets the watchdog timer count clock. wdcs is set with an 8-bit memory manipulation instruction. reset input sets wdcs to 00h. figure 11-2: timer clock select register 2 format caution: when rewriting wdcs to other data, stop the timer operation beforehand. remarks: 1. f x : main system clock oscillation frequency 2. figures in parentheses apply to operation with f x = 8.0 mhz. 76543210r/waddress after reset wdcs 0 0 0 0 0 wdcs2 wdcs1 wdcs0 r/w ff42h 00h wdcs2 wdcs1 wdcs0 overflow time of watchdog timer 000 f x /2 12 (512 s) 001 f x /2 13 (1 ms) 010 f x /2 14 (2 ms) 011 f x /2 15 (4 ms) 100 f x /2 16 (8.19 ms) 101 f x /2 17 (16.38 ms) 110 f x /2 18 (32.76 ms) 111 f x /2 20 (131 ms) 193 chapter 11 watchdog timer user?s manual u15251ee4v0ud00 (2) watchdog timer mode register (wdtm) this register sets the watchdog timer operating mode and enables/disables counting. wdtm is set with an 1-bit or an 8-bit memory manipulation instruction. reset input sets wdtm to 00h. figure 11-3: watchdog timer mode register format notes: 1. once set to 1, wdtm3 and wdtm4 cannot be cleared to 0 by software. 2. once set to 1, run cannot be cleared to 0 by software. thus, once counting starts, it can only be stopped by reset input. caution: when 1 is set in run so that the watchdog timer is cleared, the actual overflow time is up to 0.5% shorter than the time set by watchdog timer clock select register. remark: x = don't care. <7>6543210r/waddress after reset wdtm run 0 0 wdtm4 wdtm3 0 0 0 r/w fff9h 00h wdtm4 wdtm3 watchdog timer operation mode selection note 1 0x interval timer mode (maskable interrupt occurs upon generation of an overflow) 10 watchdog timer mode 1 (non-maskable interrupt occurs upon generation of an overflow) 11 watchdog timer mode 2 (reset operation is activated upon generation of an overflow) run watchdog timer operation mode selection note 2 0 count stop 1 counter is cleared and counting starts 194 chapter 11 watchdog timer user?s manual u15251ee4v0ud00 11.4 watchdog timer operations 11.4.1 watchdog timer operation when bit 4 (wdtm4) of the watchdog timer mode register (wdtm) is set to 1, the watchdog timer is operated to detect any inadvertent program loop. the watchdog timer count clock (inadvertent program loop detection time interval) can be selected with bits 0 to 2 (wdcs0 to wdcs2) of the timer clock select register (wdcs). watchdog timer starts by setting bit 7 (run) of wdtm to 1. after the watchdog timer is started, set run to 1 within the set overrun detection time interval. the watchdog timer can be cleared and count- ing is started by setting run to 1. if run is not set to 1 and the inadvertent program loop detection time is past, system reset or a non-maskable interrupt re quest is generated according to the wdtm bit 3 (wdtm3) value. the watchdog timer can be cleared when run is set to 1. the watchdog timer continues operating in the halt mode but it stops in the stop mode. thus, set run to 1 before the stop mode is set, clear the watchdog timer and then execute the stop instruc- tion. cautions: 1. the actual overrun detection time may be shorter than the set time by a maximum of 0.5%. 2. when the subsystem clock is selected for cpu clock, watchdog timer count operation is stopped. remarks: 1. f x : main system clock oscillation frequency 2. figures in parentheses apply to operation with f x = 8.0 mhz. table 11-4: watchdog timer overrun detection time wdcs2 wdcs1 wdcs0 runaway detection time 000 f x /2 12 (512 s) 001 f x /2 13 (1 ms) 010 f x /2 14 (2 ms) 011 f x /2 15 (4 ms) 100 f x /2 16 (8.19 ms) 101 f x /2 17 (16.38 ms) 110 f x /2 18 (32.76 ms) 111 f x /2 20 (131 ms) 195 chapter 11 watchdog timer user?s manual u15251ee4v0ud00 11.4.2 interval timer operation the watchdog timer operates as an interval timer which generates interrupts repeatedly at an interval of the preset count value when bit 3 (wdtm3) of the watchdog timer mode register (wdtm) is set to 0, respectively. when the watchdog timer operates as interval timer, the interrupt mask flag (tmmk4) and priority specify flag (tmpr4) are validated and the maskable interrupt request (intwdt) can be generated. among maskable interrupts, the intwdt default has the highest priority. the interval timer continues operating in the halt mode but it stops in stop mode. thus, set bit 7 (run) of wdtm to 1 before the stop mode is set, clear the interval timer and then execute the stop instruction. cautions: 1. once bit 4 (wdtm4) of wdtm is set to 1 (with the watchdog timer mode selected), the interval timer mode is not set unless reset input is applied. 2. the interval time just after setting with wdtm may be shorter than the set time by a maximum of 0.5%. 3. when the subsystem clock is selected for cpu clock, watchdog timer count operation is stopped. remarks: 1. f x : main system clock oscillation frequency 2. figures in parentheses apply to operation with f x = 8.0 mhz. table 11-5: interval timer interval time wdcs2 wdcs1 wdcs0 interval time 000 f x /2 12 (512 s) 001 f x /2 13 (1 ms) 010 f x /2 14 (2 ms) 011 f x /2 15 (4 ms) 100 f x /2 16 (8.19 ms) 101 f x /2 17 (16.38 ms) 110 f x /2 18 (32.76 ms) 111 f x /2 20 (131 ms) 196 user?s manual u15251ee4v0ud00 [memo] 197 user?s manual u15251ee4v0ud00 chapter 12 clock output control circuit 12.1 clock output control circuit functions the clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral lsi. clocks selected with the clock output selection register (cks) are output from the pcl/p23 pin. follow the procedure below to route clock pulses to the sgoa pin: (1) select the clock pulse output frequency (with clock pulse output disabled) with bits 0 to 3 (ccs0 to ccs2) of cks. (2) set the p23 output latch to 0. (3) set bit 3 (pm23) of port mode register 2 to 0 (set to output mode). (4) set bit 4 (cloe) of clock output selection register to 1. caution: clock output cannot be used when setting p23 output latch to 1. remark: when clock output enable/disable is switched, the clock output control circuit does not generate pulses with smaller widths than the original signal carries. (see the portions marked with * in figure 12-1). figure 12-1: remote controlled output application example cloe pcl/p23 * * pin output 198 chapter 12 clock output control circuit user?s manual u15251ee4v0ud00 12.2 clock output control circuit configuration the clock output control circuit consists of the following hardware. figure 12-2: clock output cont rol circuit block diagram table 12-1: clock output control circuit configuration item configuration control register clock output selection register (cks) port mode register 2 (pm2) internal bus f x f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 cloe ccs2 ccs1 ccs0 p23 output latch synchronizing circuit 4 pm23 selector clock output selection register port mode register 2 pcl /p23 199 chapter 12 clock output control circuit user?s manual u15251ee4v0ud00 12.3 clock output function control registers the following two types of registers are used to control the clock output function. clock output selection register (cks) port mode register 2 (pm2) (1) clock output selection register (cks) this register sets pcl output clock. cks is set with an 1-bit or an 8-bit memory manipulation instruction. reset input sets cks to 00h. caution: when enabling pcl output, set ccs0 to ccs2, then set 1 in cloe with an 1-bit memory manipulation instruction. figure 12-3: clock output selection register (cks) format remarks: 1. f x : main system clock oscillation frequency 2. figures in parentheses apply to operation with f x = 8.0 mhz. 765<4>3210r/waddress after reset cks 0 0 0 cloe 0 ccs2 ccs1 ccs0 r/w ff40h 00h ccs2 ccs1 ccs0 pcl output clock selection 000 f x (8 mhz) 001 f x /2 1 (4 mhz) 010 f x /2 2 (2 mhz) 011 f x /2 3 (1 mhz) 100 f x /2 4 (500 khz) 101 f x /2 5 (250 khz) 110 f x /2 6 (125 khz) 111 f x /2 7 (62.5 khz) other than above setting prohibited cloe pcl output control 0 output disable 1 output enable 200 chapter 12 clock output control circuit user?s manual u15251ee4v0ud00 (2) port mode register 2 (pm2) this register sets the port mode p2 input-output in 1-bit units. when using the p23/pcl pin for clock output fu nction, set pm23 and output latch of p23 to 0. pm2 is set with an 1-bit or an 8-bit memory manipulation instruction. reset input sets pm2 to ffh. figure 12-4: port mode register 2 format 76543210r/waddress after reset pm2 pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 r/w ff22h ffh pm2n pm2n pin input/output mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) 201 user?s manual u15251ee4v0ud00 chapter 13 a/d converter 13.1 a/d converter functions the a/d converter is an 8-bit resolution converter that converts analog inputs into digital values. it can control up to 12 analog input channels (ani0 to ani11). this a/d converter has the following functions: (1) a/d conversion with 8-bit resolution one channel of analog input is selected from ani0 to ani11, and a/d conversion is repeatedly executed with a resolution of 8-bits. each time the conversion has been completed, an interrupt request (intad) is generated. (2) power-fail detection function this function is to detect a voltage drop in the battery of an automobile. the result of a/d conver- sion (value of the adcr1 register) and the value of pft register (pft: power-fail compare thresh- old value register) are compared. if the condition for comparison is satisfied, the intad is generated. figure 13-1: a/d converter block diagram ani0/p10 ani1/p11 ani2/p12 ani3/p13 ani4/p14 selector sample & hold circuit voltage comparator successive approximation register (sar) control circuit 4 a/d conversion result register (adcr1) tap selector av dd avss intad a/d converter mode register analog input channel specification register internal bus ads12 ads11 ads10 adcs1 fr12 fr11 fr10 ani5/p15 ani6/p16 ani7/p17 ani8 ani9 ani10 ani11 ads13 av ref / 202 chapter 13 a/d converter user?s manual u15251ee4v0ud00 figure 13-2: power-fail det ection function block diagram 13.2 a/d converter configuration a/d converter consists of the following hardware. (1) successive approximation register (sar) this register compares the analog input voltage value to the voltage tap (compare voltage) value applied from the series resistor string, and holds the result from the most significant bit (msb). when up to the least significant bit (lsb) is set (end of a/d conversion), the sar contents are transferred to the a/d conversion result register. table 13-1: a/d converter configuration item configuration analog input 11 channels (ani0 to ani11) register successive approximation register (sar) a/d conversion result register (adcr1) control register a/d converter mode register (adm1) analog input channel specification register (ads1) power-fail compare mode register (pfm) power-fail compare threshold value register (pft) selector a/d converter internal bus power-fail compare mode register (pfm) comparator pfen pfcm power-fail compare threshold value register (pft) intad pfen pfcm ani0/p10 ani1/p11 ani2/p12 ani3/p13 ani4/p14 multiplexer ani5/p15 ani6/p16 ani7/p17 ani8 ani9 ani10 ani11 203 chapter 13 a/d converter user?s manual u15251ee4v0ud00 (2) a/d conversion result register (adcr1) this register holds the a/d conversion result. each time when the a/d conversion ends, the con- version result is loaded from the successive approximation register. adcr1 is read with an 8-bit memory manipulation instruction. reset input clears adcr1 to 00h. caution: if a write operation is executed to the a/d converter mode register (adm1) and the analog input channel specification register (ads1) the contents of adcr1 are unde- fined. read the conversion result before a write operation is executed to adm1 and ads1. if a timing other than the above is used, the correct conversion result may not be read. (3) sample & hold circuit the sample & hold circuit samples each analog input sequential applied from the input circuit, and sends it to the voltage comparator. this circuit holds the sampled analog input voltage value dur- ing a/d conversion. (4) voltage comparator the voltage comparator compares the analog input to the series resistor string output voltage. (5) series resistor string the series resistor string is in av dd /av ref to av ss , and generates a voltage to be compared to the analog input. (6) ani0 to ani11 pins these are twelve analog input pins to input analog signals to the a/d converter. ani0 to ani7 are alternate-function pins that can also be used for digital input. ani8 to ani11 are a/d converter analog input only pins. caution: use ani0 to ani11 input voltages within the specification range. if a voltage higher than av dd or lower than av ss is applied (even if within the absolute maximum rating range), the conversion value of that channel will be undefined and the conversion values of other channels may also be affected. (7) av dd pin (shared with av ref pin) this pin inputs the a/d converter reference voltage and is used as the power supply pin of the a/d converter. the supply power has to be connected when the a/d converter is used. it converts signals input to ani0 to ani11 into digital signals according to the voltage applied between av dd /av ref and av ss . even if the ad-converter is not used av dd /av ref has to be connected to v dd . (8) av ss pin this is the gnd potential pin of the a/d converter. always keep it at the same potential as the v ss pin even when not using the a/d converter. 204 chapter 13 a/d converter user?s manual u15251ee4v0ud00 13.3 a/d converter control registers the following 4 types of registers are used to control a/d converter. a/d converter mode register (adm1) analog input channel specification register (ads1) power-fail compare mode register (pfm) power-fail compare threshold value register (pft) (1) a/d converter mode register (adm1) this register sets the conversion time for analog input to be a/d converted, conversion start/stop and external trigger. adm1 is set with an 1-bit or an 8-bit memory manipulation instruction. reset input clears adm1 to 00h. figure 13-3: a/d converter m ode register (adm1) format note: set fr12 to fr10 so that the a/d conversion time is 14 s or more. caution: bits 0 to 2 and bit 6 must be set to 0. remark: f x : main system clock oscillation frequency <7>6543210r/waddress after reset adm1 adcs1 0 fr12 fr11 fr10 0 0 0 r/w ff98h 00h adcs1 a/d conversion operation control 0 stop conversion operation 1 enable conversion operation fr12 fr11 fr10 conversion time selection note 000 144/f x 001 120/f x 010 96/f x 100 72/f x 101 60/f x 110 48/f x other than above setting prohibited 205 chapter 13 a/d converter user?s manual u15251ee4v0ud00 (2) analog input channel specification register (ads1) this register specifies the analog voltage input port for a/d conversion. ads1 is set with an 8-bit memo ry manipulation instruction. reset input clears ads1 to 00h. figure 13-4: analog input channel sp ecification register (ads1) format caution: bits 4 to 7 must be set to 0. 76543210r/waddress after reset ads1 0 0 0 0 ads13 ads12 ads11 ads10 r/w ff99h 00h ads13 ads12 ads11 ads10 analog input channel specification 0000 ani0 0001 ani1 0010 ani2 0011 ani3 0100 ani4 0101 ani5 0110 ani6 0111 ani7 1000 ani8 1001 ani9 1010 ani10 1011 ani11 other than above setting prohibited 206 chapter 13 a/d converter user?s manual u15251ee4v0ud00 (3) power-fail compare mode register (pfm) the power-fail compare mode register (pfm) controls a comparison operation. pfm is set with an 8-bit manipulation instruction. reset input clears pfm to 00h. figure 13-5: power-fail compare mode register (pfm) format caution: bits 0 to 5 must be set to 0. (4) power-fail compare threshold value register (pft) the power-fail compare threshold value register (pft) sets a threshold value against which the result of a/d conversion is to be compared. pft is set with an 8-bit memo ry manipulation instruction. reset input clears pft to 00h. figure 13-6: power-fail compare threshold value register (pft) 76543210r/waddress after reset pfm pfen pfcm 0 0 0 0 0 0 r/w ff9ah 00h pfen enables power-fail comparison 0 disables power-fail comparison (used as normal a/d converter) 1 enables power-fail comparison (used to detect power failure) pfcm power-fail compare mode selection 0 adcr1 t pft generates interrupt request signal intad adcr1 < pft does not generate interrupt request signal intad 1 adcr1 t pft does not generate interrupt request signal intad adcr1 < pft generates interrupt request signal intad 76543210r/waddress after reset pft pft7 pft6 pft5 pft4 pft3 pft2 pft1 pft0 r/w ff9bh 00h 207 chapter 13 a/d converter user?s manual u15251ee4v0ud00 13.4 a/d converter operations 13.4.1 basic operations of a/d converter <1> select one channel for a/d conversion with the ana log input channel specification register (ads1). <2> the voltage input to the selected analog input chan nel is sampled by the sa mple & hold circuit. <3> when sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the input analog voltage is held until the a/d conversion operation is ended. <4> set bit 7 of the successive approximation register (sar) so that the tap selector sets the series resistor string voltage tap to (1/2) av dd . <5> the voltage difference between the series resistor string voltage tap and analog input is compared with the voltage comparator. if the analog input is greater than (1/2) av dd , the msb of sar remains set. if the analog input is smaller than (1/2) av dd , the msb is reset. <6> next, bit 6 of sar is automatically set, and the operation proceeds to the next comparison. the series resistor string voltage tap is selected according to the preset value of bit 7, as described below. bit 7 = 1: (3/4) av dd bit 7 = 0: (1/4) av dd the voltage tap and analog input voltage are compared and bit 6 of sar is manipulated as follows. analog input voltage t voltage tap: bit 6 = 1 analog input voltage < voltage tap: bit 6 = 0 <7> comparison is continued in th is way up to bit 0 of sar. <8> upon completion of the comparison of 8 bits, an effective digital result value remains in sar, and the result value is transferred to and latched in the a/d conversion result register (adcr1). at the same time, the a/d conversion end interrupt request (intad) can also be generated. caution: the first a/d conversion value just after starting the a/d conversion (adcs1=1) is undefined. 208 chapter 13 a/d converter user?s manual u15251ee4v0ud00 figure 13-7: basic operation of 8-bit a/d converter a/d conversion operations are performed continuously until bit 7 (adcs1) of the a/d converter mode register (adm1) is reset (to 0) by software. if a write operation to the adm1 and analog input channel specification register (ads1) is performed during an a/d conversion operation, the conversion operation is initialized, and if the adcs1 bit is set (to 1), conversion starts again from the beginning. reset input sets the a/d conversion result register (adcr1) to 00h. conversion time sampling time sampling a/d conversion undefined 80h c0h or 40h conversion result a/d converter operation sar adcr1 intad conversion result 209 chapter 13 a/d converter user?s manual u15251ee4v0ud00 13.4.2 input voltage and conversion results the relation between the analog input voltage input to the analog input pins (ani0 to ani7) and the a/d conversion result (s tored in the a/d conversion result regi ster (adcr1)) is sh own by the following expression. or where, int( ) : function which returns integer part of value in parentheses v in : analog input voltage av dd /av ref :av dd pin voltage and a/d converter power supply adcr1 : a/d conversion result register (adcr1) value adcr1 = int ( u 256 + 0.5) v in av dd (adcr1 - 0.5) u - v in < av dd 256 (adcr1 + 0.5) u av dd 256 210 chapter 13 a/d converter user?s manual u15251ee4v0ud00 figure 13-8 shows the relation between the analog input voltage and the a/d conversion result. figure 13-8: relation between analog input voltage and a/d conversion result 255 254 253 3 2 1 0 a/d conversion result (adcr1) 1 512 1 256 3 512 2 256 5 512 3 256 507 512 254 256 509 512 255 256 511 512 1 input voltage/av dd 211 chapter 13 a/d converter user?s manual u15251ee4v0ud00 13.4.3 a/d converter operation mode the operation mode of the a/d converter is the select mode. one analog input channel is selected from among ani0 to ani11 with the analog input channe l specification register (ads1) and a/d conversion is performed. the following two types of functions can be selected by setting the pfen flag of the pfm register. (1) normal 8-bit a/d converter (pfen = 0) (2) power-fail detection function (pfen = 1) (1) a/d conversion (when pfen = 0) when bit 7 (adcs1) of the a/d converter mode register (adm1) is set to 1 and bit 7 of the power- fail compare mode register (pfm) is set to 0, a/d conversion of the voltage applied to the analog input pin specified with the analog input channel specification register (ads1) starts. upon the end of the a/d conversion, the conversion result is stored in the a/d conversion result register (adcr1), and the interrup t request signal (intad) is ge nerated. after one a/d conversion operation is started and ended, the next conversion operation is immediately started. a/d conver- sion operations are repeated until new data is written to ads1. if ads1 is rewritten during a/d conversion operation, the a/d conversion operation under execu- tion is stopped, and a/d conversion of a newly selected analog input channel is started. if data with adcs1 set to 0 is written to adm1 during a/d conversion operation, the a/d conver- sion operation stops immediately. (2) power-fail detection function (when pfen = 1) when bit 7 (adcs1) of the a/d converter mode register (adm1) and bit 7 (pfen) of the power-fail compare mode register (pfm) are set to 1, a/d conversion of the voltage applied to the analog input pin specified with the analog input channel specification register (ads1) starts. upon the end of the a/d conversion, the conversion result is stored in the a/d conversion result register (adcr1), compared with the value of the power-fail compare threshold value register (pft), and intad is generated under the condition specified by the pfcm flag of the pfm regis- ter. caution: when executing power-fail comparison, the interrupt request signal (intad) is not generated on completion of the first conversion after adcs1 has been set to 1. intad is valid from completion of the second conversion. 212 chapter 13 a/d converter user?s manual u15251ee4v0ud00 figure 13-9: a/d conversion remarks: 1. n = 0, 1,..., 11 2. m = 0, 1,...,11 adm1 rewrite adcs1 = 1 ads1 rewrite adcs1 = 0 a/d conversion adcr1 intad (pfen = 0) intad (pfen = 1) anin anin anin anim anim stop anin anin anim conversion suspended; conversion results are not stored first conversion condition satisfied 213 chapter 13 a/d converter user?s manual u15251ee4v0ud00 13.5 a/d converter precautions (1) current consumption in standby mode a/d converter stops operating in the standby mode. at this time, current consumption can be reduced by setting bit 7 (adcs1) of the a/d converter mode register (adm1) to 0 to stop conver- sion. figure 13-10 shows how to reduce the current consumption in the standby mode. figure 13-10: example method of reducing current consumption in standby mode (2) input range of ani0 to ani11 the input voltages of ani0 to ani11 should be within the specification range. in particular, if a volt- age higher than av dd /av ref or lower than av ss is input (even if within the absolute maximum rat- ing range), the conversion value of that channel will be undefined and the conversion values of other channels may also be affected. (3) contending operations <1> contention between a/d co nversion result register (adcr1) wr ite and adcr1 read by instruction upon the end of conversion adcr1 read is given priority. after the read operation, the new conversion result is written to adcr1. <2> contention between adcr1 write and a/d converter mode register (adm1) write or analog input channel specification register (ads1) write upon the end of conversion adm1 or ads1 write is given priority. adcr1 wr ite is not performed, nor is the conversion end interrupt request signal (intad) generated. av dd av ss p-ch series resistor string (~ 21 k ? 214 chapter 13 a/d converter user?s manual u15251ee4v0ud00 (4) noise counter measures to maintain 8-bit resolution, attention must be paid to noise input to pin av dd and pins ani0 to ani11. because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in figure 13-11 to reduce noise. figure 13-11: analog input pin handling (5) ani0 to ani11 the analog input pins (ani0 to ani7) also function as input port pins (p10 to p17). when a/d conversion is performed with any of pins ani0 to ani7 selected, do not execute a port input instruction while co nversion is in progress, as this may reduce the conversion resolution. also, if digital pulses are applied to a pin adjacent to the pin in the process of a/d conversion, the expected a/d conversion value may not be obtainable due to coupling noise. therefore, avoid applying pulses to pins adjacent to the pin undergoing a/d conversion. (6) av dd /av ref pin input impedance a series resistor string of approximately 21 k : is connected between the av dd pin and the av ss pin. therefore, if the ou tput impedance of the refe rence voltage is hi gh, this will result in parallel con- nection to the series resistor string between the av dd pin and the av ss pin, and there will be a large reference voltage error. reference voltage input c = 100 to 1000 pf if there is a possibility that noise equal to or higher than av dd or equal to or lower than av ss may enter, clamp with a diode with a small v f value (0.3 v or lower). av dd av ss v ss ani0 to ani11 215 chapter 13 a/d converter user?s manual u15251ee4v0ud00 (7) interrupt request flag (adif) the interrupt request flag (adif) is not cleared ev en if the analog input channel specification reg- ister (ads1) is changed. caution is therefore required if a change of analog input pin is performed during a/d conversion. the a/d conversion result and conversion end interrupt request flag for the pre-change analog input may be set just before the ads1 rewrite, if the adif is read immediately after the ads1 rewrite, the adif may be set despite to the fact that the a/d conversion for the post-change analog input has not ended. when the a/d conversion is stopped and then resumed, clear adif before the a/d conversion operation is resumed. figure 13-12: a/d conversion end interrupt request generation timing remarks: 1. n = 0, 1,..., 11 2. m = 0, 1,..., 11 (8) read of a/d conversion result register (adcr1) when a write operation is executed to a/d converter mode register (adm1) and analog input channel specification register (a ds1), the contents of adcr1 are undefined. read the conversion result before write operation is executed to adm1 , ads1. if a timing other than the above is used, the correct conversion result may not be read. ads1 rewrite (start of anin conversion) a/d conversion adcr1 intad anin anin anim anim anin anin anim anim ads1 rewrite (start of anim conversion) adif is set but anim conversion has not ended. 216 chapter 13 a/d converter user?s manual u15251ee4v0ud00 13.6 cautions on emulation to perform debugging with the in-circuit emulator, the d/a converter mode register (dam0) must be set. dam0 is a register used to set the emulation board (ie-78k0-ns-p04). 13.6.1 d/a converter mode register (dam0) dam0 is necessary if the power-fail detection func tion is used. unless dam0 is set, the power-fail detection function cannot be used. dam0 is a write-only register. because the ie-78k0-ns-p04 uses an external ana log comparator and a d/a converter to implement part of the power-fail detection function, the reference voltage must be controlled. therefore, set bit 0 (dace) of dam0 to 1 when using the power-fail detection function. figure 13-13: d/a converter mode register (dam0) format cautions: 1. dam0 is a special register that must be set when debugging is performed with an in-circuit emulator. even if this register is used, the operation of the device is not affected. however, delete the instruction that manipulates this register from the program at the final stage of debugging. 2. bits 7 to 1 must be set to 0. 76543210r/waddress after reset dam00000000dacer/wff9ch00h dace reference voltage control 0 disabled 1 enabled (when power-fail detection function is used) 217 user?s manual u15251ee4v0ud00 chapter 14 serial interface sio20 14.1 serial interface sio20 functions the sio20 has the following three modes. operation stop mode 3-wire serial i/o mode (standard mode) 3-wire serial i/o mode (spi compatible mode) features: 8-bit data length simultaneous transmit and receive available start bit is fixed to msb four different transmit/receive modes with selectable clock inversion and clock phase master and slave modes receive buffer with overflow bit to detect error condition status register to monitor status of receive data buffer possibility to connect to motorola spi tm in master and slave mode (1) operation stop mode this mode is used when serial transfers are not performed. for details, see 14.5.1 ?operation stop mode? on page 225. (2) 3-wire serial i/o mode (spi compatible mode with fixed as msb first) this is an 8-bit data transfer mode using three lines: a serial clock line, serial output line (so), and serial input line (si). since simultaneous transmit and receive operations are enabled in 3-wire serial i/o mode, the processing time for data transfers is reduced. the first bit in the 8-bit data in serial transfers is fixed as the msb. the 3-wire serial interface works with additional functions to select the clock phase and the clock polarity, to see if there is new data received and error detection. after the reception of the data, the received data of the serial i/o shift register is transferred to the serial i/f receive data buffer. 3-wire serial i/o mode is useful for connection to a peripheral i/o device that includes a clock-syn- chronous serial interface, or a display controller, etc. for details, see 14.5.2 ?3-wire serial i/o mode? on page 226 (multi-functional mode). 218 chapter 14 serial interface sio20 user?s manual u15251ee4v0ud00 figure 14-1 shows the block diagram of the sio20. figure 14-1: block diagram of sio20 receive data buffer direction control serial clock counter serial clock control interrupt request selector serial i/o shift register (sio20) sdva sdof csie20 clph clpo mode0 scl201 scl200 8 8 8 8 fx/2 3 fx/2 7 tm50 intcsi20 serial i/f operating mode register si2/p20 so2/p21 sck2/p22 receive data buffer status register circuit register (sirb20) signal generator circuit 219 chapter 14 serial interface sio20 user?s manual u15251ee4v0ud00 14.2 serial interface sio20 configuration the sio20 includes the following hardware. (1) serial i/o shift register (sio20) this is an 8-bit register that performs parallel-serial conversion and serial transmit/receive (shift operations) synchronized with the serial clock. sio20 is set by an 8-bit memory manipulation instruction. when ?1? is set to bit 7 (csie20) of the serial operation mode register 20 (csim20), a serial oper- ation can be started by writing data to or reading data from sio20. when transmitting, data written to sio20 is output via the serial output (so2). when receiving, data is read from the serial input (si2) and written to sio20. the reset signal resets the register value to 00h. cautions: 1. do not access to sio20 (read/write) during transfer operation. 2. if clph is set to ?1? (clock phase shifting enabled) and the sio20 is in slave mode, the received data should not be read from the sio20 shift register directly. in this particular case, the result in the shift register does not match the transferred byte. the correct byte can be read from the receive data buffer. this has to be considered when writing software for the sio20. (2) serial i/f operation mode register (csim20) this is an 8-bit register that performs the operati on of the serial interface, the selection the clock phase and polarity and the selection of the clock source. csim20 is set by an 8-bit me mory manipulation instruction. when ?1? is set to bit 7 (csie20) of the serial operation mode register 20 (csim20), a serial oper- ation can be started by writing data to or reading data from sio20. the reset signal resets the register value to 00h. (3) serial i/f receive data buffer register (sirb20) this is an 8-bit register read only register that contains the data that has been transferred by the sio20. polling of the srbs20 register can monito r the status of this register. if an overflow occurred, the sirb20 data will no t change its contents until the st atus is read out and a new byte is transferred to sirb20. sirb20 has to be read with an 8-bit memory manipulation instruction. after reset the register value is undefined. table 14-1: configuration of sio20 item configuration registers serial i/o shift register (sio20) serial i/f receive da ta buffer (sirb20) control registers serial i/f operation mode register (csim20) receive data buffer status register (srbs20) 220 chapter 14 serial interface sio20 user?s manual u15251ee4v0ud00 (4) receive data buffer status register (srbs20) this 8-bit read only register reflects the status of the serial i/f receive data buffer (sirb20). it con- tains two flags indicating that there is unread data in the receive data buffer or that there is an overflow error. srbs20 can be read with an 8-bit memory manipulation instruction. the reset signal resets the register value to 00h. (a) sdva ? serial data valid flag this read-only bit indicates, that the serial interface receive data buffer (sirb20) contains unread information from a transmission. sdva can only be cleared by reading the receive buffer sirb. once the sirb20 is read, sdva remains cleared until the next byte enters the sirb20. (b) sdof ? overflow flag this read-only register indicates an overflow error in the sirb20. if the sirb contains unread data (sdva = ?1?), and another byte fully enters the shift register, this flag is automatically set, indicating that data will be lost. the unread data from a previous trans- mission can still be read out of the sirb20, since t he sirb20 is not updated in case of an overflow condition. reading the srbs20 clears the sdof flag. srbs20 can be read with an 1-bit or an 8-bit memory manipulation instruction. the reset signal resets the register value to 00h. caution: even if the sio is in overflow state, it generates an interrupt request, every time a new (lost) byte has completely entered the shift register. 14.3 serial interface sio20 list of sfrs (special function registers) table 14-2: list of sfrs (special function registers) sfr name symbol r/w units available for bit manipulation value after reset 1-bit 8-bit 16-bit serial i/f operation mode register csim20 r/w u u ? 00h receive data buffer status register srbs20 r ? u ? 00h serial i/f receive data buffer sirb20 r ? u ? undefined serial i/o shift register sio20 r/w ? u ? 00h 221 chapter 14 serial interface sio20 user?s manual u15251ee4v0ud00 14.4 serial interface control registers the sio20 uses the following type of register for control functions. serial operation mode register 20 (csim20) receive data buffer status register 20 (sbrs20) (1) serial i/f operation mode register 20 (csim20) this register is used to enable or disable serial interface channel 3?s serial clock, operation modes, and specific operations. csim20 can be set via an 1-bit or an 8-bit memory manipulation instruction. the reset input sets the value to 00h. figure 14-2: serial operation mode register (csim20) format (1/2) <7>6543210r/waddress after reset csim20 csie20 0 0 clph clpo mode0 scl201 scl200 r/w ffa8h 00h csie20 enable/disable specification for sio20 shift register operation serial counter port note 1 0 operation stop clear port function 1 operation enable count operation enable serial function + port function clph clock phase selection 0 normal mode (msb is output on the first valid edge of sck2) 1 phase mode (msb is valid before the first valid edge of sck2) clpo clock polarity selection 0 normal mode (send data changes on the falling edge of sck2) 1 inverted mode (send data changes on the rising edge of sck2) mode0 transfer operation modes and flags operation mode transfer start trigger p21/so2 0 transmit/receive mode write to sio20 so2 output 1 receive-only mode note 2 read from sio20 port function 222 chapter 14 serial interface sio20 user?s manual u15251ee4v0ud00 figure 14-2: serial operation mode register (csim20) format (2/2) notes: 1. when csie20 = 0 (sio20 operation stop status), the pins connected to si2 and s02 can be used for port functions. 2. when mode0 = 1 (receive mode), pin p21 can be used for port function. cautions: 1. bits 5 and 6 must be set to 0. 2. while a serial transfer operation is enabled (csie20 = 1), be sure to stop the serial transfer operation once before changing the values of bits other than csie20 to different data. 3. when operation is disabled (csie20 = 0) during a serial transfer operation, the operation will be stopped immediately. at this time, even if operation is enabled again (csie20 = 1) after it was once stopped, the operation will not start. to resume operation, set operation enable (csie20 = 1) and then execute an access that will be the start trigger of each transfer operation mode. 4. changing csie20 and other bits at the same time is prohibited. after clearing csie20 to 0, change the other bits. remark: f x : main system clock oscillation frequency scl201 scl200 clock selection 0 0 external clock input 0 1 8-bit timer register (tm50) 10 f x /2 3 11 f x /2 7 223 chapter 14 serial interface sio20 user?s manual u15251ee4v0ud00 the following shows the relationships between the clpo and clph settings, and the serial transfer clock, data output, and input data capture timing. figure 14-3: serial transfer operation timi ng according to clpo and clph settings remarks: 1. sck2 : serial transfer clock 2. so2: data output timing 3. si2: input data capture timing clpo clph serial transfer operation clock selection 00 01 10 11 d7 d6 d5 d4 d3 d2 d1 d0 sck2 so2 si2 d7 d6 d5 d4 d3 d2 d1 d0 sck2 so2 si2 d7 d6 d5 d4 d3 d2 d1 d0 sck2 so2 si2 d7 d6 d5 d4 d3 d2 d1 d0 sck2 so2 si2 224 chapter 14 serial interface sio20 user?s manual u15251ee4v0ud00 (2) receive data buffer status register (srbs20) this register reflects that there is unread data in the serial receive data buffer register or that there is in an overflow error. srbs20 can be read via an 8-bit memory manipulation instruction. reset input sets the value to 00h. figure 14-4: receive data buffer status register (srbs20) format (3) serial i/f data buffer register (sirb20) this register contains the data that has been transferred by the sio20. sirb20 can be read by an 8-bit memory manipulation instruction. reset input sets the value to undefined. figure 14-5: serial i/f data buffer register (sirb20) 76543210r/waddress after reset srbs20 0 0 0 0 0 0 sdva sdof r ffaah 00h sdva serial data valid 0 no valid data in serial i/f receive data buffer 1 valid data in serial i/f receive data buffer sdof serial data transfer overflow 0 no overflow error 1 overflow error: receive data buffer full 76543210r/waddress after reset sirb20 sirb207 sirb206 sirb205 sirb204 sirb 203 sirb202 sirb201 sirb200 r ffa9h undef. 225 chapter 14 serial interface sio20 user?s manual u15251ee4v0ud00 14.5 operations the sio20 has the following two operation modes. operation stop mode 3-wire serial i/o mode 14.5.1 operation stop mode this mode does not perform serial transfers and can therefore reduce power consumption. in operation stop mode the pins connected to sck2, si2 and so2 can be used for port functions. (1) register settings operation stop mode is set via serial operation mode register 20 (csim20). csim20 can be set via 1-bit or 8-bit memory manipulation instructions. the reset input sets the value to 00h. figure 14-6: format of serial op eration mode register (csim20) note: when csie20 = 0 (sio20 operation stop status ), the pins connected to sck2, si2 and so2 can be used for port functions. <7>6543210r/waddress after reset csim20 csie20 0 0 clph clpo mode0 scl201 scl200 r/w ffa8h 00h csie20 sio20 operation enable/disable specification shift register operation serial counter port note 0 operation stop clear port function 1 operation enable count operation enable serial function + port function 226 chapter 14 serial interface sio20 user?s manual u15251ee4v0ud00 14.5.2 3-wire serial i/o mode 3-wire serial i/o mode is useful when connecting to a peripheral i/o device that includes a clock-syn- chronous serial interface, a display controller, etc. this mode executes data transfers via three lines: a serial clock line (sck2), serial output line (so2) and serial input line (si2). (1) register settings operation stop mode is set via serial operation mode register 20 (csim20). csim20 can be set via 1-bit or 8-bit memory manipulation instructions. the reset input sets the value to 00h. figure 14-7: serial operation mode register (csim20) format notes: 1. when csie20 = 0 (sio20 operation stop status), the pins connected to si2 and s02 can be used for port functions. 2. when mode0 = 1(receive mode), pin p21 can be used for port function. <7>6543210r/waddress after reset csim20 csie20 0 0 clph clpo mode0 scl201 scl200 r/w ffa8h 00h csie20 enable/disable specification for sio20 shift register operation serial counter port note 1 0 operation stop clear port function 1 operation enable count operation enable serial function + port function clph clock phase selection 0 normal mode (msb is output on the first valid edge of sck2) 1 phase mode (msb is valid before the first valid edge of sck2) clpo clock polarity selection 0 normal mode (send data changes on the falling edge of sck2) 1 inverted mode (send data changes on the rising edge of sck2) mode0 transfer operation modes and flags operation mode transfer start trigger p21/so2 0 transmit/receive mode write to sio20 so2 output 1 receive-only mode note 2 read from sio20 port function scl201 scl200 clock selection 0 0 external clock input 0 1 8-bit timer register (tm50) 10 f x /2 3 11 f x /2 7 227 chapter 14 serial interface sio20 user?s manual u15251ee4v0ud00 the following shows the relationships between the clpo and clph settings, and the serial transfer clock, data output, and input data capture timing. figure 14-8: serial transfer operation timi ng according to clpo and clph settings remarks: 1. sck2: serial transfer clock 2. so2: data output timing 3. si2: input data capture timing clpo clph serial transfer operation clock selection 00 01 10 11 d7 d6 d5 d4 d3 d2 d1 d0 sck2 so2 si2 d7 d6 d5 d4 d3 d2 d1 d0 sck2 so2 si2 d7 d6 d5 d4 d3 d2 d1 d0 sck2 so2 si2 d7 d6 d5 d4 d3 d2 d1 d0 sck2 so2 si2 228 chapter 14 serial interface sio20 user?s manual u15251ee4v0ud00 (2) receive data buffer status register (srbs20) this register reflects that there is unread data in the serial receive data buffer register or that there is in an overflow error. srbs20 can be read via an 8-bit memory manipulation instruction. reset input sets the value to 00h. figure 14-9: receive data buffer status register (srbs20) format (3) serial i/f data buffer register (sirb20) this register contains the data that has been transferred by the sio20. sirb20 can be read by an 8-bit memory manipulation instruction. reset input sets the value to undefined. figure 14-10: serial i/f data buffer register (sirb20) 76543210r/waddress after reset srbs20 0 0 0 0 0 0 sdva sdof r ffaah 00h sdva serial data valid 0 no valid data in serial i/f receive data buffer 1 valid data in serial i/f receive data buffer sdof serial data transfer overflow 0 no overflow error 1 overflow error: receive data buffer full 76543210r/waddress after reset sirb20 sirb207 sirb206 sirb205 sirb204 sirb 203 sirb202 sirb201 sirb200 r ffa9h undef. 229 chapter 14 serial interface sio20 user?s manual u15251ee4v0ud00 (4) transfer start serial transfer starts when the following two conditions have been satisfied. transmit/receive mode when csie20 = 1 and mode0 = 0, transfer starts when writing to sio20. receive-only mode when csie20 = 1 and mode0 = 1, transfer starts when reading from sio20. caution: the transfer of the serial interface will not start when the data is written to sio20 if before csie20 bit is set to ?1?. completion of an 8-bit transfer automatically stops the serial transfer operation and the interrupt request flag is set. (5) operation mode (a) master mode the sio operates in master mode, when one of the flags scl201 and scl200 is set. only a master sio can initiate transmissions. transmission starts from a master sio by reading or writing to the sio20 data register. the byte begins shifting out on the so2 pin under the control of the serial clock. the scl201 and scl200 bits determine the speed of the transmission. through the sck2 pin the master also controls th e shift register of the slave peripheral. as the byte shifts out on the so2 pin of the master, another byte shifts in from the slave on the master?s si2 pin. the transmission ends when all eight bits are shifted out. at the end of the trans- mission the interrupt intcsi20 is triggered. (b) slave mode the sio operates in slave mode when both, the scl201 and scl200 flag are cleared and the external clock is selected. in slave mode the sck2 pin is the input for the serial clock from the master serial interface. in a slave sio, data enters the shift register under the control of the serial clock from the master serial interface. after a byte is received to the shift register of a slave sio, it is transferred to the receive data buffer, the sdva flag is set and an interrupt intcsi20 is trig- gered. to prevent an overflow condition, the slave?s software must then read the sio data register before another byte fully enters the shift register. the frequency of the sck2 for a sio20 that has configuration as slave does not have to corre- spond to any particular baud rate. a slave must complete a write to the shift register at least one bus cycle before the master starts the transmission. when the clock phase bit clph is cleared, the first edge of sck2 starts the transmission. when clph is set, reading or writing (dependi ng on mode0 flag) will start the transmission. note: sck2 must be in clear idle state before the slave is enabled to prevent sck2 from appearing as a clock edge. 230 chapter 14 serial interface sio20 user?s manual u15251ee4v0ud00 (6) transmission formats during a sio transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). a serial clock line synchronizes shifting and sampling on the two serial data lines. (a) clock phase and polarity by software any of four combination of serial clock (sck) phase and polarity can be selected, using two bits in the sio20 control register. the clock polarity is specified by the clpo control bit, which selects an active high or low clock and has no significant effect on the transmission format. the clock phase (clph) control bit selects on of two fundamentally different transmission formats. the clock phase and polarity have to be identical for the master sio device and the slave device. (b) transmission format when clph =?0? figure 14-11 shows a sio transmission with the clph control bit set to ?0?. two waveforms are shown for sck one for clpo = ?1? and another one for clpo = ?0?. the so signal is the signal out- put from the master and the si is the signal output from the slave. when clph is ?0?, the master begins driving the msb at its so pin on the first active edge (either positive or negative, depending on the setting of clpo). therefore the slave uses the first sck edge as a start transmission trigger. figure 14-11: transmission protocol for clph = 0 msb lsb do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 msb lsb 0 1 clpo so si sck sck capture strobe 231 chapter 14 serial interface sio20 user?s manual u15251ee4v0ud00 (c) transmission format when clph = ?1? figure 14-12 shows a sio transmission in which cl ph is set to ?1?. two waveforms are shown for sck, one for clpo = ?1? and another one for clpo = ?0?. the so pin is the output from the master and the si pin is the output from the slave. when clph = ?1?, the first sck edge is the msb cap- ture strobe. therefore, the slave must begin driving its data before the first sck edge. to achieve this, the slave starts driving its msb just after a write access to its shift register. figure 14-12: transmission format for clph = 1 msb lsb do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 msb lsb 1 clpo si so capture strobe 0 (output from master, input to slave's si) (input to master, output from slave's so) write operation to shift register of slave sck sck 232 chapter 14 serial interface sio20 user?s manual u15251ee4v0ud00 (7) hardware detectable error condition (overflow error) the overflow flag (sdof) is set if the sio20 re ceive data buffer (sirb20) still contains unread data from a previous transmission when the capture strobe of the lsb of the next transmission occurs (see figure 15-13). if an overflow occurs, the data being received is not transferred to the receive data buffer so that th e unread data can still be read. ther efore, an overflow error always indicates the loss of data. when reading the srbs2 0 register the sdof bits will be clear ed. to view the status of the sio20, the srbs20 register should be polled every time there is an interrupt triggered by the sio20, after reading the sirb20. figure 14-13: overflow error conditions remark: ? 233 chapter 14 serial interface sio20 user?s manual u15251ee4v0ud00 (8) operation during standby modes (a) halt mode operation the sio20 remains active after the execution of a halt instruction. in halt mode the sio20 module registers are not accessible by the cpu. if the intcsi20 interrupt is enabled it can bring the cpu out of halt mode, if a transmission is completed. if the sio20 functions are not required during halt mode, disabling the sio20 module before executing the halt instruction can reduce the power consumption. (b) stop mode operation the sio20 can operate in stop mode, if it has configuration in slave mode. after receive of a byte has finished, the sio20 triggers the intcsi20 interrupt, that can, if enabled, bring the device out of stop mode. 234 user?s manual u15251ee4v0ud00 [memo] 235 user?s manual u15251ee4v0ud00 chapter 15 serial interface sio30 15.1 sio30 functions the sio30 has the following three modes. operation stop mode 3-wire serial i/o mode 2-wire serial i/o mode. (1) operation stop mode this mode is used if serial transfer is not performed. for details, see 15.5.1 ?operation stop mode? on page 240 . (2) 3-wire serial i/o mode (fixed as msb first) this is an 8-bit data transfer mode using three lines: a serial clock line (sck3 ), serial output line (so3), and serial input line (si3). since simultaneous transmit and receive operations are enabled in 3-wire serial i/o mode, the processing time for data transfers is reduced. the first bit in the 8-bit data in serial transfers is fixed as the msb. 3-wire serial i/o mode is useful for connection to a peripheral i/o device that includes a clock-syn- chronous serial interface, like a display controller, etc. for details see 15.5.2 ?three-wire serial i/o mode? on page 241 . (3) 2-wire serial i/o mode (fixed as msb first) this is an 8-bit data transfer mode using three lines: a serial clock line (sck3 ) and a serial data input/output line (sio3). the first bit in the 8-bit data in serial transfers is fixed as the msb. 236 chapter 15 serial interface sio30 user?s manual u15251ee4v0ud00 figure 15-1 shows a block diagram of the sio30. figure 15-1: block diagram of sio30 internal bus 8 8 direction control circuit serial clock control circuit serial clock counter interruption request signal generator selector serial i/o shift register 30 (sio30) si3/p67 so3/sio3/p66 sck3/p65 intcsi30 tm50 f x /2 3 f x /2 7 csie30 mode30 scl301 scl300 register csim30 selector 237 chapter 15 serial interface sio30 user?s manual u15251ee4v0ud00 15.2 sio30 configuration the sio30 includes the following hardware. (1) serial i/o shift register (sio30) this is an 8-bit register that performs parallel-serial conversion and serial transmit/receive (shift operations) synchronized with the serial clock. sio30 is set by an 8-bit memory manipulation instruction. when ?1? is set to bit 7 (csie30) of the serial operation mode register (csim30), a serial operation can be started by writing data to or reading data from sio30. when transmitting, data written to sio30 is output via the serial output (so30). when receiving, data is read from the serial input (si30) and written to sio30. the reset signal resets the register value to 00h. caution: do not access sio30 during a transmit operation unless the access is triggered by a transfer start. 15.3 list of sfrs (special function registers) table 15-1: composition of sio30 item configuration registers serial i/o sh ift register (sio30) control registers serial operation mode register (csim30) serial mode switch register (sioswi) table 15-2: list of sfrs (special function registers) sfr name symbol r/w units available for bit manipulation value after reset 1-bit 8-bit 16-bit serial operation mode register csim30 r/w u u -00h serial i/o shift register sio30 r/w - u -00h serial mode switch register sioswi r/w u u -00h 238 chapter 15 serial interface sio30 user?s manual u15251ee4v0ud00 15.4 serial interface control register the sio30 uses the following type of register for control functions. serial operation mode register (csim30) serial mode switch register (sioswi) (1) serial operation mode register (csim30) this register is used to enable or disable the serial clock, selects operation modes, and defines specific operations. csim30 can be set via an 1-bit or an 8-bit memory manipulation instruction. the reset input sets the value to 00h. figure 15-2: format of serial op eration mode register (csim30) notes: 1. when csie30 = 0 (sio30 operation stop status), the pins connected to si3 and so3 can be used for port functions. 2. the bits 2 to 6 have to be set to 0. <7>6543210r/waddress after reset csim30 csie30 0 0 0 0 0 scl301 scl300 r/w ffafh 00h csie30 enable/disable specification for sio30 shift register operation serial counter port note 1 0 operation stop clear port function 1 operation enable count operation enable serial operation + port function scl301 scl300 clock selection (f x = 8.00 mhz) 0 0 external clock input to sck3 0 1 8-bit timer tm50 input 10 f x /2 3 11 f x /2 7 239 chapter 15 serial interface sio30 user?s manual u15251ee4v0ud00 (2) serial mode switch register (sioswi) this register is used to select the sio31's 3-wire mode or 2-wire mode data communication mode. sioswi is set by an 1-bit or an 8-bit memory manipulation instruction. the reset input sets sioswi to 00h. figure 15-3: format of serial m ode switch register (sioswi) the following operation modes and start trigger have to be set for the usage of the 3-wire mode or the 2-wire mode data communication mode. 76543210r/waddress after reset sioswi 0 0 0 0 0 0 0 sioswi r/w ffaeh 00h sioswi sio30 - serial mode switch 0 3-wire mode (reset) 1 2-wire mode table 15-3: operating modes and start trigger 3-wire or 2-wire mode of sio30 (sioswi) operation mode flag operation mode start trigger port function 2-wire mode transmit/receive mode sio30 write p65: sck3 p66: sio3 3-wire mode transmit/receive mode sio30 write p65: sck3 p66: so3 p67: si3 240 chapter 15 serial interface sio30 user?s manual u15251ee4v0ud00 15.5 serial interface operations this section explains three modes of sio30. 15.5.1 operation stop mode this mode is used if the serial transfers are not performed to reduce power consumption. during the operation stop mode, the pins can be used as normal i/o ports as well. register settings the operation stop mode can be set via the serial operation mode register (csim30). csim30 can be set via an 1-bit or an 8-bit memory manipulation instructions. the reset input sets the value to 00h. figure 15-4: format of serial op eration mode register (csim30) note: when csie30 = 0 (sio30 operation stop status), the pins si3, so3 and sck3 can be used for port functions. <7>6543210r/waddress after reset csim30 csie30 0 0 0 0 0 scl301 scl300 r/w ffafh 00h csie30 sio30 operation enable/d isable specification shift register operation serial counter port 0 operation stop clear port function note 1 1 operation enable count operation enable serial operation + port function note 2 241 chapter 15 serial interface sio30 user?s manual u15251ee4v0ud00 15.5.2 three-wire serial i/o mode the three-wire serial i/o mode is useful when conn ecting a peripheral i/o device that includes a clock-synchronous serial interface, a display controller, etc. this mode executes the data transfer vi a three lines: a serial clock line (sck3 ), serial output line (so3), and serial input line (si3). (1) register settings the 3-wire serial i/o mode is set via serial operation mode register (csim30). csim30 can be set via an 1-bit or an 8-bit memory manipulation instructions. the reset input set the value to 00h. figure 15-5: format of serial op eration mode register (csim30) notes: 1. when csie30 = 0 (sio30 operation stop status), the pins si3, so3 and sck3 can be used for port functions. 2. the bits 2 to 6 have to be set to 0. caution: in the 3-wire serial i/o mode, set the port mode register as required. set the output latch of the port to 0. <7>6543210r/waddress after reset csim30 csie30 0 0 0 0 0 scl301 scl300 r/w ffafh 00h csie30 enable/disable specification for sio30 shift register operation serial counter port 0 operation stop clear port function note 1 1 operation enable count operation enable serial operation + port function note 2 scl301 scl300 clock selection (f x = 8.00 mhz) 0 0 external clock input to sck3 0 1 8-bit timer tm50 input 10 f x /2 3 11 f x /2 7 242 chapter 15 serial interface sio30 user?s manual u15251ee4v0ud00 243 chapter 15 serial interface sio30 user?s manual u15251ee4v0ud00 15.5.3 two-wire serial i/o mode the two-wire serial i/o mode is useful when c onnecting a peripheral i/o device that includes a clock-synchronous serial interface, a display controller, etc. this mode executes the data transfer via two lines: a serial clock line (sck3 ) and serial input/output line (sio3). (1) register settings the 2-wire serial i/o mode is set via serial operation mode register 30 (csim30). csim30 can be set via an 1-bit or an 8-bit memory manipulation instructions. the reset input set the value to 00h. figure 15-7: format of serial op eration mode register (csim30) note: when csie30 = 0 (sio30 operation stop status), the pins sio3 and sck3 can be used for port functions. caution: in the 2-wire serial i/o mode, set the port mode register as required. set the output latch of the port to 0. <7>6543210r/waddress after reset csim30 csie30 0 0 0 0 0 scl301 scl300 r/w ffafh 00h csie30 enable/disable specification for sio30 shift register operation serial counter port 0 operation stop clear port function note 1 1 operation enable count operation enable serial operation + port function note 2 scl301 scl300 clock selection (f x = 8.00 mhz) 0 0 external clock input to sck3 0 1 8-bit timer tm50 input 10 f x /2 3 11 f x /2 7 244 chapter 15 serial interface sio30 user?s manual u15251ee4v0ud00 245 chapter 15 serial interface sio30 user?s manual u15251ee4v0ud00 (3) 3-wire communication operations in the three-wire serial i/o mode, data is transmitted and received in 8-bit units. each bit of data is sent or received synchronized with the serial clock. the serial i/o shift register (sio 30) is shifted synchronized with th e falling edge of the serial clock. the transmission data is held in the so3 latch and is transmitted from the so3 pin. the data is received via the si3 pin synchronized with the rising edge of the serial clock is latched to sio30. the completion of an 8-bit transfer automatically stops operation of sio30 and sets a serial trans- fer completion flag. figure 15-9: timing of three-wire serial i/o mode (4) 2-wire communication operations in the two-wire serial i/o mode, data is transmitted and received in 8-bit units. each bit of data is sent or received synchronized with the serial clock. the serial i/o shift register (sio 30) is shifted synchronized with th e falling edge of the serial clock. the transmission data is held in the sio3 latch and is transmitted from the sio3 pin. the data is received via the sio3 pin synchronized with the rising edge of the serial clock is latched to sio3. the completion of an 8-bit transfer automatically stops operation of sio3 and sets interrupt request flag. figure 15-10: timing of two-wire serial i/o mode si3 di7 di6 di5 di4 di3 di2 di1 di0 serial transfer completion flag sck3 1 so3 do7 do6 do5 do4 do3 do2 do1 do0 2345678 transfer completion transfer starts in synchronized with the serial clock?s falling edge data input sio3 di7 di6 di5 di4 di3 di2 di1 di0 serial transfer completion flag sck3 1 data output sio3 do7 do6 do5 do4 do3 do2 do1 do0 2345678 transfer completion transfer starts in synchronized with the serial clock?s falling edge 246 chapter 15 serial interface sio30 user?s manual u15251ee4v0ud00 (5) transfer start a serial transfer starts when the following conditions have been satisfied and transfer data has been set to serial i/o shift register 30 (sio30). the sio30 operation control bit must be set (csie = 1) in transmit/receive mode when csie30 = 1, transfer starts when writing to sio30. caution: after the data has been written to sio30, the transfer will not start even if the csie30 bit value is set to ?1?. the completion of an 8-bit transfer automatically stops the serial transfer operation and sets a serial transfer completion flag. after an 8-bit serial transfer, the internal serial clock is either stopped or is set to high level. 247 user?s manual u15251ee4v0ud00 chapter 16 serial in terface channel uart 16.1 uart functions the serial interface uart has the following two modes. (1) operation stop mode this mode is used if the serial transfer is performed to reduce power consumption. for details, see 16.5.1 operation stop mode . (2) asynchronous serial interface (uart) mode this mode enables the full-duplex operation where one byte of data is transmitted and received after the start bit. the on-chip dedicated uart baud rate generator enables communications using a wide range of selectable baud rates. for details, see 16.5.2 asynchronous serial interface (uart) mode . figure 16-1 shows a block diagram of the uart macro. figure 16-1: block diagram of uart internal bus receive buffer rxb0 rxd/p24 txd/p25 receive shift register pe0 fe0 ove0 asis0 txs0 intser intst baud rate generator f x /2 - f x /2 8 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 asim0 intsr receive control parity check transmit shift register transmit control parity addition rxs0 248 chapter 16 serial interface channel uart user?s manual u15251ee4v0ud00 16.2 uart configuration the uart includes the following hardware. (1) transmit shift register 1 (txs0) this register is for setting the transmit data. the data is written to txs0 for transmission as serial data. when the data length is set as 7 bits, bits 0 to 6 of the data written to txs0 are transmitted as serial data. writing data to txs0 starts the transmit operation. txs0 can be written via 8-bit memory manipulation instructions. it cannot be read. when reset is input, its value is ffh. cautions: 1. do not write to txs0 during a transmit operation. 2. the same address is assigned to txs0 and the receive buffer register (rxb0). a read operation reads values from rxb0. (2) receive shift register 1 (rxs0) this register converts serial data input via the rxd pin to parallel data. when one byte of the data is received at this register, the receive data is transferred to the receive buffer register (rxb0). rxs0 cannot be manipulated directly by a program. (3) receive buffer register (rxb0) this register is used to hold receive data. when one byte of data is received, one byte of new receive data is transferred from the receive shift register (rxs0). when the data length is set as 7 bits, receive data is sent to bits 0 to 6 of rxb0. the msb must be set to ?0? in rxb0. rxb0 can be read to via 8-bit memory manipulation instructions. it cannot be written to. when reset is input, its value is ffh. caution: the same address is assigned to rxb0 and the transmit shift register (txs0). during a write operation, values are written to txs0. table 16-1: configuration of uart item configuration registers transmit shift register 1 (txs0) receive shift re gister 1 (rxs0) receive buffer register (rxb0) control registers asynchronous serial interface mode register (asim0) asynchronous serial interface status register (asis0) baud rate generator control register (brgc0) 249 chapter 16 serial interface channel uart user?s manual u15251ee4v0ud00 (4) transmission control circuit the transmission control circuit controls transmit o perations, such as adding a start bit, parity bit, and stop bit to data that is written to the transmit shift register (txs0), based on the values set to the asynchronous serial interface mode register (asim0). (5) reception control circuit the reception control circuit controls the receive operations based on the values set to the asyn- chronous serial interface mode register (asim0). during a receive operation, it performs error checking, such as parity errors, and sets various values to the asynchronous serial interface sta- tus register (asis0) according to the type of error that is detected. 16.3 list of sfrs (special function registers) table 16-2: list of sfrs (special function registers) sfr name symbol r/w units available for bit manipu- lation value when reset 1-bit 8-bit 16-bit transmit shift register txs0 w - u -ffh receive buffer register rxb0 r asynchronous serial interface mode register asim0 r/w u u - 00h asynchronous serial interf ace status register asis0 r - u - baud rate generator control register brgc0 r/w - u - 250 chapter 16 serial interface channel uart user?s manual u15251ee4v0ud00 16.4 serial interface control registers the uart uses the following three types of registers for control functions. asynchronous serial interface mode register (asim0) asynchronous serial interface status register (asis0) baud rate generator control register (brgc0) (1) asynchronous serial interface mode register (asim0) this is an 8-bit register that controls the uart serial transfer operation. asim0 can be set by an 1-bit or an 8-bit memory manipulation instructions. reset input sets the value to 00h. figure 16-2 shows the format of asim0. figure 16-2: format of asynchronous serial interface mode register (asim0) (1/2) 76543210r/waddress after reset asim0 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 0 r/w ffa0h 00h txe0 rxe0 operation mode rxd0/p62 pin function txd0/p63 pin function 0 0 operation stop port function port function 01 uart0 mode (receive only) serial operation port function 10 uart0 mode (transmit only) port function serial operation 11 uart0 mode (transmit and receive) serial operation serial operation ps01 ps00 parity bit specification 0 0 no parity 01 zero parity always added during transmission no parity detection during reception (parity errors do not occur) 1 0 odd parity 1 1 even parity cl0 character length specification 0 7 bits 1 8 bits 251 chapter 16 serial interface channel uart user?s manual u15251ee4v0ud00 figure 16-2: format of asynchronous serial interface mode register (asim0) (2/2) caution: before writing different data to asim0, please note the following instructions: 1. never rewrite bits 6 or 7 (rxe0 and txe0) during a transmit operation. wait until transmit operation is completed. 2. during a receive operation you may change rxe0 only. but note that the receive operation will be stopped immediately and the contents of rxb0 and asis0 do not change, nor does intsr0 or intser0 occur. 3. never change bits 1 to 5 (isrm0 to ps01) unless bits 6 and 7 (rxe0 and txe0) were cleared to 0 before. bit 0 must always be 0. sl0 stop bit length specification for transmit data 01 bit 12 bits isrm0 receive completion interrupt control when error occurs 0 receive completion interrupt is issued when an error occurs 1 receive completion interrupt is not issued when an error occurs 252 chapter 16 serial interface channel uart user?s manual u15251ee4v0ud00 (2) asynchronous serial interface status register (asis0) when a receive error occurs during uart mode, this register indicates the type of error. asis0 can be read using an 8-bit memory manipulation instruction. when reset is input, its value is 00h. figure 16-3: format of asynchronous serial interface status register (asis0) notes: 1. even if a stop bit length of two bits has been set to bit 2 (sl0) in the asynchronous serial interface mode register (asim0), the stop bit detection during a receive operation only applies to a stop bit length of 1 bit. 2. be sure to read the contents of the receive buffer register (rxb0) when an overrun error has occurred. until the contents of rxb0 ar e read, further overru n errors will occur when receiving data. 76543210r/waddress after reset asis0 0 0 0 0 0 pe0 fe0 ove0 r ffa1h 00h pe0 parity error flag 0 no parity error 1 parity error (incorrect parity bit detected) fe0 framing error flag 0 no framing error 1 framing error note 1 (stop bit not detected) fe0 overrun error flag 0 no overrun error 1 overrun error note 2 (next receive operation was completed before data was read from receive buffer register) 253 chapter 16 serial interface channel uart user?s manual u15251ee4v0ud00 (3) baud rate generator control register (brgc0) this register sets the serial clock for uart. brgc0 can be set via an 8-bit memory manipulation instruction. when reset is input, its value is 00h. figure 16-4 shows the format of brgc0. figure 16-4: format of baud rate generator control register (brgc0) (1/2) (f x = 8.00 mhz) 76543210r/waddress after reset brgc0 0 tps02 tps01 tps00 mdl03 mdl02 mdl01 mdl00 r/w ffa2h 00h tps02 tps01 tps00 source clock selection for 5-bit counter n 000 f x /2 1 1 001 f x /2 2 2 010 f x /2 3 3 011 f x /2 4 4 100 f x /2 5 5 101 f x /2 6 6 110 f x /2 7 7 111 f x /2 8 8 254 chapter 16 serial interface channel uart user?s manual u15251ee4v0ud00 figure 16-4: format of baud rate generator control register (brgc0) (2/2) caution: writing to brgc0 when rxe0 and / or txe0 are set to 1 (receive and / or transmit operation selected) may cause abnormal output from the baud rate generator and disable further communication operations. therefore do write to brgc0 only when rxe0 and txe0 are set to 0. remarks: 1. f sck : source clock for 5-bit counter 2. n: value set via tps00 to tps02 (1 d n d 8) 3. k: value set via mdl00 to mdl03 (0 d k d 14) mdl03 mdl02 mdl01 mdl00 input clock selection for baud rate generator k 0000 f sck /16 0 0001 f sck /17 1 0010 f sck /18 2 0011 f sck /19 3 0100 f sck /20 4 0101 f sck /21 5 0110 f sck /22 6 0111 f sck /23 7 1000 f sck /24 8 1001 f sck /25 9 1010 f sck /26 10 1011 f sck /27 11 1100 f sck /28 12 1101 f sck /29 13 1110 f sck /30 14 1 1 1 1 setting prohibited - 255 chapter 16 serial interface channel uart user?s manual u15251ee4v0ud00 16.5 serial interface operations this section explains the different modes of the uart. 16.5.1 operation stop mode this mode is used when serial transfer is performed to reduce power consumption. in the operation stop mode, pins can be used as ordinary ports. register settings operation stop mode settings are made via the asynchronous serial interface mode register (asim0). asim0 can be set via an 1-bit or an 8-bit memory manipulation instructions. when reset is input, its value is 00h. figure 16-5: register settings caution: before writing different data to asim0, please note the following instructions: 1. never rewrite bits 6 or 7 (rxe0 and txe0) during a transmit operation. wait until transmit operation is completed. 2. during a receive operation you may change rxe0 only. but note that the receive operation will be stopped immediately and the contents of rxb0 and asis0 do not change, nor does intsr0 or intser0 occur. 3. never change bits 1 to 5 (isrm0 to ps01) unless bits 6 and 7 (rxe0 and txe0) were cleared to 0 before. bit 0 must always be 0. <7><6>543210r/waddress after reset asim0 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 0 r/w ffa0h 00h txe0 rxe0 operation mode rxd0/p62 pin function txd0/p63 pin function 0 0 operation stop port function port function 01 uart0 mode (receive only) serial operation port function 10 uart0 mode (transmit only) port function serial operation 11 uart0 mode (transmit and receive) serial operation serial operation 256 chapter 16 serial interface channel uart user?s manual u15251ee4v0ud00 16.5.2 asynchronous serial interface (uart) mode this mode enables full-duplex operation where one byte of the data is transmitted or received after the start bit. the on-chip dedicated uart baud rate generator enables communications by using a wide range of selectable baud rates. (1) register settings the uart mode settings are made via the asynchronous serial interface mode register (asim0), asynchronous serial interface status register (asis0), and the baud rate generator control register (brgc0). (a) asynchronous serial interface mode register (asim0) asim0 can be set by 1-bit or 8-bit memory manipulation instructions. when reset is input, its value is 00h. figure 16-6: format of asynchronous serial interface mode register (asim0) (1/2) <7><6>543210r/waddress after reset asim0 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 0 r/w ffa0h 00h txe0 rxe0 operation mode rxd0/p62 pin function txd0/p63 pin function 0 0 operation stop port function port function 01 uart0 mode (receive only) serial operation port function 10 uart0 mode (transmit only) port function serial operation 11 uart0 mode (transmit and receive) serial operation serial operation ps01 ps00 parity bit specification 0 0 no parity 01 zero parity always added during transmission no parity detection during reception (parity errors do not occur) 1 0 odd parity 1 1 even parity cl0 character length specification 0 7 bits 1 8 bits 257 chapter 16 serial interface channel uart user?s manual u15251ee4v0ud00 figure 16-6: format of asynchronous serial interface mode register (asim0) (2/2) caution: before writing different data to asim0, please note the following instructions: 1. never rewrite bits 6 or 7 (rxe0 and txe0) during a transmit operation. wait until transmit operation is completed. 2. during a receive operation you may change rxe0 only. but note that the receive operation will be stopped immediately and the contents of rxb0 and asis0 do not change, nor does intsr0 or intser0 occur. 3. never change bits 1 to 5 (isrm0 to ps01) unless bits 6 and 7 (rxe0 and txe0) were cleared to 0 before. bit 0 must always be 0. sl0 stop bit length specification for transmit data 01 bit 12 bits isrm0 receive completion interrupt control when error occurs 0 receive completion interrupt is issued when an error occurs 1 receive completion interrupt is not issued when an error occurs 258 chapter 16 serial interface channel uart user?s manual u15251ee4v0ud00 (b) asynchronous serial interface status register (asis0) asis0 can be read using an 8-bit memory manipulation instruction. when reset is input, its value is 00h. figure 16-7: format of asynchronous serial interface status register (asis0) notes: 1. even if a stop bit length of two bits has been set to bit 2 (sl0) in the asynchronous serial interface mode register (asim0), the stop bit detection during a receive operation only applies to a stop bit length of 1 bit. 2. be sure to read the contents of the receive buffer register (rxb0) when an overrun error has occurred. until the contents of rxb0 ar e read, further overru n errors will occur when receiving data. 76543210r/waddress after reset asis0 0 0 0 0 0 pe0 fe0 ove0 r ffa1h 00h pe0 parity error flag 0 no parity error 1 parity error (incorrect parity bit detected) fe0 framing error flag 0 no framing error 1 framing error note 1 (stop bit not detected) ove0 overrun error flag 0 no overrun error 1 overrun error note 2 (next receive operation was completed before data was read from receive buffer register) 259 chapter 16 serial interface channel uart user?s manual u15251ee4v0ud00 (c) baud rate generator control register (brgc0) brgc0 can be set via an 8-bit memory manipulation instruction. when reset is input, its value is 00h. figure 16-8: format of baud rate generator control register (brgc0) (1/2) (f x = 8.00 mhz) 76543210r/waddress after reset brgc0 0 tps02 tps01 tps00 mdl03 mdl02 mdl01 mdl00 r/w ffa2h 00h tps02 tps01 tps00 source clock selection for 5-bit counter n 000 f x /2 1 1 001 f x /2 2 2 010 f x /2 3 3 011 f x /2 4 4 100 f x /2 5 5 101 f x /2 6 6 110 f x /2 7 7 111 f x /2 8 8 260 chapter 16 serial interface channel uart user?s manual u15251ee4v0ud00 figure 16-8: format of baud rate generator control register (brgc0) (2/2) caution: writing to brgc0 when rxe0 and / or txe0 are set to 1 (receive and / or transmit operation selected) may cause abnormal output from the baud rate generator and disable further communication operations. therefore do write to brgc0 only when rxe0 and txe0 are set to 0. remarks: 1. f sck : source clock for 5-bit counter 2. n: value set via tps00 to tps02 (1 d n d 8) 3. k: value set via mdl00 to mdl03 (0 d k d 14) mdl03 mdl02 mdl01 mdl00 input clock selection for baud rate generator k 0000 f sck /16 0 0001 f sck /17 1 0010 f sck /18 2 0011 f sck /19 3 0100 f sck /20 4 0101 f sck /21 5 0110 f sck /22 6 0111 f sck /23 7 1000 f sck /24 8 1001 f sck /25 9 1010 f sck /26 10 1011 f sck /27 11 1100 f sck /28 12 1101 f sck /29 13 1110 f sck /30 14 1 1 1 1 setting prohibited - 261 chapter 16 serial interface channel uart user?s manual u15251ee4v0ud00 the transmit/receive clock that is used to generate the baud rate is obtained by dividing the main system clock. baud rate setting the main system clock is divided to generate the transmit/receive clock. the baud rate generated by the main system clock is determined according to the following formula. f x : oscillation frequency of main system clock in mhz n : value set via tps00 to tps02 (1 d n d 8) for details, see table 16-3. k : value set via mdl00 to mdl02 (0 d k d 14) in register brgc0 the relation between the 5-bit counter?s source clock assigned to bits 4 to 6 (tps00 to tps02) of brgc0 and the ?n? value in the above formula is shown in figure 16-4, ?format of baud rate generator control register (brgc0) (1/2),? on page 253. remark: f x : oscillation frequency of main system clock. table 16-3: relation between 5-bit counter?s source clock and ?n? value tps02 tps01 tps00 source clock selection for 5-bit counter n 000 f x /2 1 1 001 f x /2 2 2 010 f x /2 3 3 011 f x /2 4 4 100 f x /2 5 5 101 f x /2 6 6 110 f x /2 7 7 111 f x /2 8 8 [baud rate] = f x 2 n+1 (k + 16) [kbps] 262 chapter 16 serial interface channel uart user?s manual u15251ee4v0ud00 error tolerance range for baud rates the tolerance range for baud rates depends on the number of bits per frame and the counter?s division rate [1/(16 + k)]. table 16-4 describes the relation between the main system clock and the baud rate and figure 16-9 shows an example of a baud rate error tolerance range. remarks: 1. f x : oscillation frequency of main system clock 2. n: value set via tps00 to tps02 (1 d n d 8) 3. k: value set via mdl00 to mdl03 (0 d k d 14) figure 16-9: error tolerance (when k = 0), including sampling errors caution: the above tolerance value is the value calculated based on the ideal sample point. in the actual design, allow margins that include errors of timing for detecting a start bit. remark: t: 5-bit counter?s source clock cycle table 16-4: relation between main system clock and baud rate baud rate (bps) f x = 8.386 mhz f x = 8.000 mhz f x = 5.000 mhz f x = 4.1943 mhz brgco err (%) brgco err (%) brgco err (%) brgco err (%) 600 7bh 1.10 7ah 0.16 70h 1.73 6bh 1.14 1200 6bh 1.10 6ah 0.16 60h 1.73 5bh 1.14 2400 5bh 1.10 5ah 0.16 50h 1.73 4bh 1.14 4800 4bh 1.10 4ah 0.16 40h 1.73 3bh 1.14 9600 3bh 1.10 3ah 0.16 30h 1.73 2bh 1.14 19200 2bh 1.10 2ah 0.16 20h 1.73 1bh 1.14 31250 21h -1.34 20h 0 14h 0 11h -1.31 38400 1bh 1.10 1ah 0.16 10h 1.73 0bh 1.14 76800 0bh 1.10 0ah 0.16 00h 1.73 - - 115200 02h 1.10 01h 2.12 ---- basic timing (clock cycle t) start d0 d7 p stop high-speed clock (clock cycle t?) enabling normal reception start d0 d7 p stop low-speed clock (clock cycle t?) enabling normal reception start d0 d7 p stop 32t 64t 256t 288t 320t 352t ideal sampling point 304t 336t 30.45t 60.9t 304.5t 15.5t 15.5t 0.5t sampling error 33.55t 67.1t 301.95t 335.5t baud rate error tolerance (when k = 0) = = 4.8438 (%) 15.5 u 100 320 263 chapter 16 serial interface channel uart user?s manual u15251ee4v0ud00 (2) communication operations (a) data format as shown in figure 16-10, the format of the transmit/receive data consists of a start bit, character bits, a parity bit, and one or more stop bits. the asynchronous serial interface mode register (asim0) is used to set the character bit length, parity selection, and stop bit length within each data frame. figure 16-10: format of transmit/receive data in asynchronous serial interface start bit............. 1 bit character bits... 7 bits or 8 bits parity bit........... even parity, odd parity, zero parity, or no parity stop bit(s)........ 1 bit or 2 bits when ?7 bits? is selected as the number of character bits, only the low-order 7 bits (bits 0 to 6) are valid. in this case during a transmission the highest bit (bit 7) is ignored and during reception the highest bit (bit 7) must be set to ?0?. the asynchronous serial interface mode register (asim0) and the baud rate generator control register (brgc0) are used to set the serial transfer rate. if a receive error occurs, information about the receive error can be recognized by reading the asynchronous serial interface status register (asis0). d0 d1 d2 d3 d4 d5 d6 d7 start bit parity bit stop bit 1 data frame 264 chapter 16 serial interface channel uart user?s manual u15251ee4v0ud00 (b) parity types and operations the parity bit is used to detect bit errors in transfer data. usually, the same type of parity bit is used by the transmitting and receiving sides. when odd parity or even parity is set, errors in the parity bit (the odd-number bit) can be detected. when zero parity or no parity is set, errors are not detected. even parity during transmission the number of bits in transmit data that includes a parity bit is controlled so that there are an even number of ?1? bits. the value of the parity bit is as follows. if the transmit data contains an odd number of ?1? bits: the parity bit value is ?1?. if the transmit data contains an even number of ?1? bits: the parity bit value is ?0? during reception the number of ?1? bits is counted among the transfer data that include a parity bit, and a parity error occurs when the result is an odd number. odd parity during transmission the number of bits in transmit data that includes a parity bit is controlled so that there is an odd number of ?1? bits. the value of the parity bit is as follows. if the transmit data contains an odd number of ?1? bits: the parity bit value is ?0? if the transmit data contains an even number of ?1? bits: the parity bit value is ?1? during reception the number of ?1? bits is counted among the transfer data that include a parity bit, and a parity error occurs when the result is an even number. zero parity during transmission, the parity bit is set to ?0? regardless of the transmit data. during reception, the parity bit is not checked. therefore, no pa rity errors will occur regardless of whether the parity bit is a ?0? or an ?1?. no parity no parity bit is added to the transmit data. during reception, receive data is regarded as having no parity bit. since there is no parity bit, no parity errors will occur. 265 chapter 16 serial interface channel uart user?s manual u15251ee4v0ud00 (c) transmission the transmit operation is started when transmit data is written to the transmit shift register (txs0). a start bit, parity bit, and stop bit(s) are automatically added to the data. starting the transmit operation shifts out the data in txs0, thereby emptying txs0, after which a transmit completion interrupt (intst0) is issued. the timing of the transmit completion interrupt is shown in figure 16-11. figure 16-11: timing of asynchronous serial interface transmit completion interrupt caution: do not write to the asynchronous serial interface mode register (asim0) during a transmit operation. writing to asim0 during a transmit operation may disable further transmit operations (in such cases, enter a reset to restore normal operation). whether or not a transmit operation is in progress can be determined via software using the transmit completion interrupt (intst0) or the interrupt request flag (stif) that is set by intst0. txd (output) d0 d1 d2 d6 d7 parity stop start intst (i) stop bit length: 1 bit txd (output) d0 d1 d2 d6 d7 parity start intst (ii) stop bit length: 2 bits stop 266 chapter 16 serial interface channel uart user?s manual u15251ee4v0ud00 (d) reception the receive operation is enabled when bit 6 (rxe0) of the asynchronous serial interface mode register (asim0) is set to "1", and input data via rxd pin is sampled. the serial clock specified by asim0 is used when sampling the rxd pin. when the rxd pin goes low, the 5-bit counter begi ns counting, the start timing signal for data sampling is output if half of the specified baud rate time has elapsed. if the sampling of the rxd0 pin input of this start timing signal yields a low-level result, a start bit is recognized, after which the 5-bit counter is initialized and starts counting and data sampling begins. after the start bit is recog- nized, the character data, parity bit, and one-bit stop bit are detected, at which point reception of one data frame is completed. once the reception of one data frame is completed, the receive data in the shift register is trans- ferred to the receive buffer register (rxb0) and a receive completion interrupt (intsr0) occurs. even if an error has occurred, the receive data in which the er ror occurred is still transferred to rxb0 and intsr0 occurs (see figure 14-9). if the rxe0 bit is reset (to ?0?) during a receive operation, the receive operation is stopped imme- diately. at this time, neither the contents of rxb0 and asis0 will change, nor does intsr0 or intser0 occur. figure 16-12 shows the timing of the asynchronous serial interface receive completion interrupt. figure 16-12: timing of asynchronous serial interface receive completion interrupt cautions: 1. be sure to read the contents of the receive buffer register (rxb0) even when a receive error has occurred. overrun errors will occur during the next data receive operations and the receive error status will remain until the contents of rxb0 are read. 2. if the receive operation is enabled with the rxd0 pin at the low level, the receive operation is immediately aborted. make sure that the rxd0 pin input is at the high level before enabling the receive operation. rxd (input) d0 d1 d2 d6 d7 parity stop start intsr 267 chapter 16 serial interface channel uart user?s manual u15251ee4v0ud00 (e) receive errors three types of errors can occur during a receive operation: parity error, framing error, or overrun error. if, as the result of the data reception, an error flag is set to the asynchronous serial interface status register (asis0), a receive error interrupt (intser0) will occur. receive erro r interrupts are generated before receive interrupts (intsr0). table 16-5 lists the causes of receive errors. as part of the receive error interrupt (intser0) servicing, the contents of asis0 can be read to determine which type of error occurred during the receive operation (see table 16-5 and figure 16-13). the content of asis0 is reset (to ?0?) if the receive buffer register (rxb0) is read or when the next data is received (if the next data contains an error, another er ror flag will be set). figure 16-13: receive error timing cautions: 1. the contents of asis0 are reset (to ?0?) when the receive buffer register (rxb0) is read or when the next data is received. to obtain information about the error, be sure to read the contents of asis0 before reading rxb0. 2. be sure to read the contents of the receive buffer register (rxb0) even when a receive error has occurred. overrun errors will occur during the next data receive operations and the receive error status will remain until the contents of rxb0 are read. table 16-5: causes of receive errors receive error cause asis0 value parity error parity specified during transmission does not match parity of receive data 04h framing error stop bit was not detected 02h overrun error reception of the next data was completed before data was read from the receive buffer register 01h rxd (input) d0 d1 d2 d6 d7 parity stop start intsr intser intser (when parity error occurs) 268 chapter 16 serial interface channel uart user?s manual u15251ee4v0ud00 16.6 standby function serial transfer operations can be performed during halt mode. during stop mode, serial transfer operations are stopped and the values in the asynchronous serial interface mode register (asim0), the transmit shift register (txs0), the receive shift register (rxs0), and the receive buffer register (rxb0) remain as they were just before the clock was stopped. output from the txd pin retains the immediately previous data if the clock is stopped (if the system enters stop mode) during a transmit operation. if the clock is stopped during a receive operation, the data received before the clock was stopped is retained and all subsequent operations are stopped. the receive operation can be restarted once the clock is restarted. 269 user?s manual u15251ee4v0ud00 chapter 17 can controller table 17-1: outline of the function feature details protocol can2.0 with active extended frame capability (bosch specification 2.0 part b) baudrate max. 500 kbps at 8 mhz clock supply bus line control cmos in / out for external transceiver clock selected by register data storage cpu ram area with shared access dcan uses up to 288 byte of ram unused bytes can be used by cpu for other tasks message organisation received messages will be stored in ram area depending on message identifier transmit messages have two dedicated buffers in ram area message number one input receive shadow buffer (not readable by user) up to 16 receive message objects including 2 masks two transmit channels message sorting unique identifier on all 16 receive message objects up to 2 message objects with mask global mask for all messages dcan protocol sfr acce ss for general control interrupt transmit interrupt for each channel one receive interrupt with enable control for each message one error interrupt time functions support of time stamp and global time system programmable single shot mode diagnostic readable error counters ?valid protocol activity flag? for verification of bus connection ?receive only? mode for automatic baudrate detection power down modes sleep mode: wake up from can bus stop mode: no wake-up from can bus 270 chapter 17 can controller user?s manual u15251ee4v0ud00 17.1 can protocol can is an abbreviation of "c ontroller a rea n etwork", and is a class c high speed multiplexed communi- cation protocol. can is specified by bosch in the can specification 2.0 from september 1991 and is standardized in iso-11 898 (international organization for stan dardization) and sae (society of auto- motive engineers). 17.1.1 protocol mode function (1) standard format mode this mode supports an 11-bit message identifier thus making it possible to differentiate between 2048 types of messages. (2) extended format mode in the extended format mode, the identifier has 29 bits. it is built by the standard identifier (11 bits) and an extended identifier (18 bits). when the ide bits of the arbitration field is "rece ssive", the frame is sent in the extended format mode. when a message in extended format mode and a remote frame in standard format mode are simultaneously transmitted, the node transmitting the message with the standard mode wins the arbitration. (3) bus values the bus can have one of two complementary logical values: "dominant" or "recessive". during simultaneous transmission of "dominant" and "recessive" bits , the resulting bus value will be "dominant" (non destructive arbitration). for example, in case of a wired-and implementation of the bus, the ?dominant? level would be represented by a logical ?0? and the ?recessi ve? level by a logical ?1?. this specific representation is used in this manual. physical states (e.g. electrical voltage, light) that represent the logical levels are not given in this document. 17.1.2 message format the can protocol message supports different types of frames. the types of frames are listed below: data frame: carries the data from a transmitter to the receiver. remote frame: transmission demand frame from the requesting node. error frame: frame sent on error detection. overload frame: frame sent when a data or remote frame would be overwritten by the next one before the receiving node could process it. the reception side did not finish its operations on the reception of the previously received frame yet. 271 chapter 17 can controller user?s manual u15251ee4v0ud00 17.1.3 data frame / remote frame figure 17-1: data frame figure 17-2: remote frame remark: this frame is transmitted when the reception no de requests transmission. data field is not transmitted even if the data length code z '0' in the control field. c bus idle d e g h i j k k f ( ) ( ) ( ) interframe space end of frame ack field crc field data field control field arbitration field start of frame data frame r d 1 (11 + 1) (29 + 3) 6 0 ... 64 16 2 73 c d e g h i j k k ( ) ( ) ( ) bus idle interframe space end of frame ack field crc field control field arbitration field start of frame remote frame r d 272 chapter 17 can controller user?s manual u15251ee4v0ud00 17.1.4 description of each field (1) "r" indicates recessive level. "d" indicates dominant level. start of frame: the start of data frame and remote frame are indicated. figure 17-3: data frame the start of frame (sof) is denoted by the falling edge of the bus signal. reception continues when 'dominant level' is detected at the sample point. the bus becomes idle state when 'recessive level' is detected at a sample point. (2) arbitration field: sets priority, specifies data frame or remote frame, and defines the protocol mode. figure 17-4: arbitration field/standard format mode start of frame r d 1 bit interframe space on bus idle arbitration field rtr (1 bit) control field arbitration field ide (1 bit) r0 identifier id28 . . . id18 (11 bits) r d 273 chapter 17 can controller user?s manual u15251ee4v0ud00 figure 17-5: arbitration field/extended format mode id28 - id0 is the identifier. the identifier is transmitted with msb at first position. substitute remote request (srr) is only used in extended format mode and is always recessive. table 17-2: bit number of the identifier table 17-3: rtr setting table 17-4: mode setting protocol mode identifier number standard format mode 11 bits extended format mode 29 bits frame type rtr bit data frame 0 remote frame 1 protocol mode ide bit standard format mode 0 extended format mode 1 srr (1 bit) control field arbitra tion field ide (1 bit) r0 identifier id28 . . . id18 (11 bits) identifier id17 . . . id0 (18 bits) rtr (1 bit) r1 r d 274 chapter 17 can controller user?s manual u15251ee4v0ud00 (3) control field: the data byte number dlc in the data field specifies the number of data bytes in the current frame (dlc=0 to 8). figure 17-6: control field (standard format mode) figure 17-7: control field (extended format mode) the bits r0 and r1 are reserved bits for future use and are recommended to be recessive. table 17-5: data length code setting remark: in case of a remote frame, the data field is not generated even if data length code z '0'. data length code dlc3 dlc2 dlc1 dlc0 number of data bytes 0000 0 0001 1 0111 7 1xxx 8 rtr control field arbitration field ide r0 data field r d dlc3 dlc2dlc1dlc0 rtr control field arbitration field r1 r0 data field r d dlc3 dlc2dlc1dlc0 275 chapter 17 can controller user?s manual u15251ee4v0ud00 (4) data field: this field carries the data bytes to be sent. the number of data bytes is defined by the dlc value. figure 17-8: data field (5) crc field: this field consists of a 15-bit crc sequence to check the transmission error and a crc delimiter. figure 17-9: crc field 15 bits crc generation polynomial is expressed by p(x) = x 15 + x 14 + x 10 + x 8 + x 7 + x 4 + x 3 + 1. transmission node: transmits the crc sequence ca lculated from the start of frame, arbitration field, control field and data field eliminating stuff bits. reception node: the crc received will be compared with the crc calculated in the receiving node. for this calculation the stuff bits of the received crc are eliminated. in case these do not match, the node issues an error frame. data (8 bits) data field control field crc field r d data (8 bits) crc sequence (15 bits) crc field data field and control field ack field r d crc delimiter (1 bit) 276 chapter 17 can controller user?s manual u15251ee4v0ud00 (6) ack field: for check of normal reception. figure 17-10: ack field receive node sets the ack slot to dominant level if no error was detected. (7) end of frame: indicates the end of the transmission/reception. figure 17-11: end of frame ack slot (1 bit) ack field crc field end of frame r d ack delimiter (1 bit) (7 bits) end of frame ack field interframe space of overload frame r d 277 chapter 17 can controller user?s manual u15251ee4v0ud00 (8) interframe space: this sequence is inserted after data frames, remote frames, error frames, and overload frames in the serial bitstream on the bus to indicate start or end of a frame. the length of the interframe space depends on the error state (active or passive) of the node. (a) error active: consists of 3 bits intermission and bus idle. figure 17-12: interframe space/error active (b) error passive: consists of 3 bits inte rmission, suspend transmission and bus idle. figure 17-13: interframe space/error passive remark: the nominal value of the intermission field is 3 bits. however, transmission nodes may start immediately a transmission already in the 3 rd bit of this field when a dominant level is detected. table 17-6: operation in the error state error state operation error active any node in this state is able to start a transmission whenever the bus is idle. error passive any node in this state has to wait for 11 co nsecutive recessive bits before initiating a transmission. intermission (3 bits) interframe space any frame any frame r d bus idle (0 to f bits) suspend transmission (8 bits) interframe space each frame each frame r d bus idle intermission (3 bits) (0 to f bits) 278 chapter 17 can controller user?s manual u15251ee4v0ud00 17.1.5 error frame this frame is sent from a node if an error is detected. the type of an error frame is defined by its error flag: active error flag or passive error flag. which kind of flag a node transmits after detecting an error condition depends on the internal count of the error counters of each node. figure 17-14: error frame table 17-7: definition of each field no. name bit number definition 1 error flag 6 error active node: sends 6 bits dominant level continuously. error passive node: sends 6 bits recessive level continuously. 2 error flag superpositioning 0 to 6 nodes receiving an ?error flag? detect bit stuff errors and issue error flags? themselves. 3 error delimiter 8 sends 8 bits recessive level continuously. in case of monitoring dominant level at 8th bit, an overload frame is transmitted after the next bit. 4 erroneous bit - an error frame is transmitted contin uously after the bit where the error has occurred (in case of a crc error, transmission continues after the ack delimiter). 5 interframe space/ overload frame 3/14 20 max interframe space or overload frame continues. c d e f g ( ) ( ) error frame interframe space or overload frame error delimiter error flag error bit r d error flag 279 chapter 17 can controller user?s manual u15251ee4v0ud00 17.1.6 overload frame this frame is started at the first bit of the intermission when the reception node is busy with exploiting the receive operation and is not ready for further reception. when a bit error is detected in the intermission, also an overload frame is sent following the next bit after the bit error detection. detecting a dominant bit during the 3 rd bit of intermission will be interpreted as start of frame. at most two overload frames may be gener ated to delay the next data frame or remote frame. figure 17-15: overload frame table 17-8: definition of each frame no. name bit number definition 1 overload flag 6 sent 6 bits dominant level continuously. 2 overload flag from any node 0 to 6 a node that receives an overload flag in the interframe space. issues an overload flag. 3 overload delimiter 8 sends 8 bits recessive level continuously. in case of monitoring dominant level at 8th bit, an overload frame is transmitted after the next bit. 4any frame - output following the end of frame, error delimiter and overload delimiter. 5 interframe space/ overload frame 3/14 20 max interframe space or overload frame continues. c d e f g ( ) ( ) overload frame interframe space or overload frame overload delimiter overload flag superpositioning (node n) overload flag (node m) each frame r d 280 chapter 17 can controller user?s manual u15251ee4v0ud00 17.2 function 17.2.1 arbitration if two or more nodes happen to start transmission in coincidence, the access conflict is solved by a bit- wise arbitration mechanism during transmission of the arbitration field. (1) when a node starts transmission: during bus idle, the node having the output data can transmit. (2) when more than one node starts transmission: the node with the lower identifier wins the arbitration. any transmitting node compares its output arbitration field and the data level on the bus. it looses arbitration, when it sends recessive level and reads dominant from bus. table 17-9: arbitration (3) priority of data frame and remote frame: when a data frame and remote frame with the same message identifier are on the bus, the data frame has priority because its rtr bit carries 'dominant level'. the data frame wins the arbitration. 17.2.2 bit stuffing when the same level continues for more than 5 bits, bit stuffing (insert 1 bit with inverse level) takes place. due to this a resynchronization of the bit timing can be done at least every 10 bits. nodes detecting an error condition send an error fr ame, violating the bit stuff rule and indicating this message to be erroneous for all nodes. table 17-10: bit stuffing level detection status of arbitrating node conformity of level continuous transmission non-conformity of level the data output is stopped from the next bit and reception operation starts. transmission during the transmission of a data frame and a remote frame, when the same level continues for 5 bits in the data between the start of frame and the ack field, 1 bit level with reverse level of data is inserted before the following bit. reception during the reception of a data frame and a remote frame, when the same level continues for 5 bits in the data between the start of frame and the ack field, the reception is continued by deleting the next bit. 281 chapter 17 can controller user?s manual u15251ee4v0ud00 17.2.3 multi master as the bus priority is determined by the identifier, any node can be the bus master. 17.2.4 multi cast any message can be received by any node (broadcast). 17.2.5 sleep mode/stop function this is a function to put the can controller in waiting mode to achieve low power consumption. the sleep mode of the dcan complies to th e method described in iso 11898. additional to this sleep mode, which can be woken up by bus activities, the stop mode is fully con- trolled by the cpu device. 282 chapter 17 can controller user?s manual u15251ee4v0ud00 17.2.6 error control function (1) error types table 17-11: error types (2) output timing of the error frame table 17-12: output timing of the error frame (3) measures when error occurs transmission node re-transmits the data frame or the remote frame after the error frame. the can standard (iso-11898) allows a programmable suppression of this re-transmission. it is called single shot mode. ty p e description of error detection state detection method detection condition transmission/ reception field/frame bit error comparison of output level and level on the bus (except stuff bit) disagreement of both levels transmission/ reception node bit that output dat a on the bus at the start of frame to the end of frame, error frame and overload frame. stuff error check of the reception data at the stuff bit 6 consecutive bits of the same output level transmission/ reception node start of frame to crc sequence crc error comparison of the crc generated from the reception data and the received crc sequence disagreement of crc reception node start of frame to data field form error field/frame check of the fixed format detection of the fixed for- mat error reception node crc delimiter ack field end of frame error frame overload frame ack error check of the ack slot by the transmission node detection of recessive level in ack slot transmission node ack slot type output timing bit error, stuff error, form error, ack error error frame is started at the next bit timing following the detected error error passive crc error error frame is started at the next bit timing following the ack delimiter 283 chapter 17 can controller user?s manual u15251ee4v0ud00 (4) error state (a) types of error state three types of error state: these are error active, error passive and bus off. the transmission error counter (tec) and the reception error counter (rec) control the error state. the error counters are incremented on each error occurrence (refer to table 3-6). if the value of error counter exceeds 96, warning level for error passive state is reached. when only one node is active at start-up, it may not receive an acknowledgment on a transmitted message. this will in crement tec until error passive state is reached. the bus off state will not be reached because for this specific condition te c will not increment any more if values greater than 127 are reached. a node in bus off state will not issue any dominant level on the can transmit pin. the reception of messages is not affected by the bus off state. table 17-13: types of error type operation value of error counter output error flag type error active transmission/ reception 0 to 127 active error flag (6 bits of dominant level continue) error passive transmission 128 to 255 passive error flag (6 bits of recessive level continue) reception 128 or more bus off transmission more than 255 communication cannot be made reception - does not exist 284 chapter 17 can controller user?s manual u15251ee4v0ud00 (b) error counter error counter counts up when an error has occurred, and counts down upon successful transmission and reception. the error counters are updated during the first bit of an error flag. table 17-14: error counter (c) overload frame in case the recessive leve l of first intermission bit is driven to dominant level, an overload frame occurs on the bus. upon detection of an over load frame any transmit request will be postponed until the bus becomes idle. state transmission error counter (tec) reception error counter (rec) reception node detects an error (except bit error in the active error flag or overload flag). no change +1 reception node detects dominant leve l following the error flag of the own error frame. no change +8 transmission node transmits an error flag. exception: 1. ack error is detected in the error passive state and domi- nant level is not detected in the passive error flag sent. 2. stuff error generation in arbitration field. +8 no change bit error detection during active error flag and overload flag when transmitting node is in error active state. +8 no change bit error detection during active error flag and overload flag when receiving node is in error active state. no change +8 when the node detects fourteen continuous dominant bits counted from the beginning of the active error flag or the over- load flag, and every time, eight subsequent dominant bits after that are detected. every time when the node detects eight continuous dominant bits after the pa ssive error flag. +8 +8 when the transmitting node has completed to sent without error. -1 (-0 when error counter = 0) no change when the reception node has completed to receive without error. no change -1 (1 d rec d 127) ?0 (rec = 0) 119-127 (rec > 127) 285 chapter 17 can controller user?s manual u15251ee4v0ud00 17.2.7 baud rate control function (1) nominal bit time (8 to 25 time quanta) definition of 1 data bit time is as follows. figure 17-16: nominal bit time (8 to 25 time quanta) sync segment: in this segment the bit synchronization is performed. prop segment: this segment absorbs delays of the output buffer, the can bus and the input buffer. prop segment time = (output buffer delay) + (can bus delay) + (input buffer delay). phase segment 1/2: these segments compensate the data bit time error. the larger the size measured in tq is, the larger is the tolerable error. the synchronization jump width (sjw) specif ies the synchronization range. the sjw is programmable. sjw can have less or equal number of tq as phase segment 2. table 17-15: segment name and segment length note: ipt = information processing time. it needs to be less than or equal to 2 tq. segment name segment length (allowed number of tqs) sync segment (synchronization segment) 1 prop segment (propagation segment) programmable 1 to 8 phase segment 1 (phase buffer segment 1) programmable 1 to 8 phase segment 2 (phase buffer segment 2) maximum of phase segment 1 and the ipt note sjw programmable 1 to 4 sync segment prop segment phase segment 1 phase segment 2 nominal bit time sjw sjw sample point [1 minimum time for one time/quantum (tq) = 1/fx] 286 chapter 17 can controller user?s manual u15251ee4v0ud00 (2) adjusting synchronization of the data bit the transmission node transmits data synchronized to the transmission node bit timing. the reception node adjusts synchronization at recessive to dominant edges on the bus. depending on the protocol this synchronizat ion can be a hard or soft synchronization. (a) hard synchronization this type of synchronization is performed when the reception node detects a start of frame in the bus idle state. when the node detects a fallin g edge of a sof, the curren t time quanta becomes the synchronization segment. the length of the following segments are defined by the values programmed into the sync0 and sync1 registers. figure 17-17: adjusting synchronization of the data bit sync segment prop segment phase segment 1 phase segment 2 can bus bit timing bus idle start of frame 287 chapter 17 can controller user?s manual u15251ee4v0ud00 (b) soft synchronization when a recessive to dominant level change on the bus is detected, a soft synchronization is performed. if the phase error is la rger than the programme d sjw value, the node will adjust the timing by applying this sjw-value. full synchronization is achieved by subsequent adjustments on the next recessive to dominant edge(s). these errors that are equal or less of the programmed sjw are corrected instantly and full synchronization is achieved already for the next bit. the tq at which the edge occurs becomes sync segment forcibly, if the phase error is less than or equal to sjw. figure 17-18: bit synchronization sync segment prop segment phase segment -sjw sync segment prop segment phase segment 2 +sjw 288 chapter 17 can controller user?s manual u15251ee4v0ud00 17.2.8 state shift chart figure 17-19: transmission state shift chart start of frame arbitration field data field control field crc field ack field end of frame intermission 1 error frame overload frame bus idle intermission 2 c a b initialization setting reception reception reception end rtr = 0 end end end end error active bit error rtr = 1 bit error bit error bit error ack error bit error bit error end end bit error form error error passive 8 bits of '1' start of frame reception start of frame transmission 289 chapter 17 can controller user?s manual u15251ee4v0ud00 figure 17-20: reception state shift chart start of frame arbitration field data field control field crc field ack field end of frame intermission 1 error frame overload frame bus idle a c initialization setting transmission transmission b transmission end rtr = 0 end end end end rtr = 1 stuff error stuff error crc error, stuff error ack error, bit error bit error, form error bit error end end not ready form error start of frame transmission start of frame reception stuff error not ready 290 chapter 17 can controller user?s manual u15251ee4v0ud00 figure 17-21: error state shift chart (a) transmission (b) reception error active bus off error passive tec > 128 tec > 256 tec < 127 tec = 0 tec = transmission error counter error active error passive rec > 128 rec = reception error counter rec < 127 291 chapter 17 can controller user?s manual u15251ee4v0ud00 17.3 outline description figure 17-22: structural block diagram this interface part handles all protocol activities by hardware in the can protocol part. the memory access engine fetches information for the can protocol transmission from the dedicated ram area to the can protocol part or compares and sorts incoming information and stores it into predefined ram areas. the dcan interfaces directly to the ram area that is accessible by the dcan and by the cpu. the dcan part works with an external bus transceiver which converts the transmit data and receive data lines to the electrical char acteristics of the can bus itself. can protocol interface management (includes global registers) memory access engine cpu high speed ram receive messages memory buffer ram dcan-interface bus arbitration logic cpu access receive messages receive messages receive messages transmit buffers transmit buffers timer external transceiver canl canh sfr time stamp signal 292 chapter 17 can controller user?s manual u15251ee4v0ud00 17.4 connection with target system the dcan macro has to be connected to the can bus with an external transceiver. figure 17-23: connection to the can bus 17.5 can controller configuration the can-module consists of the following hardware . table 17-16: can configuration item configuration message definition in ram area can input/output 1 (ctxd) 1 (crxd) control registers can control register (canc) transmit control register (tcr) receive message register (rmes) redefinition control register (redef) can error status register (canes) transmit error counter (tec) receive error counter (rec) message count register (mcnt) bit rate prescaler (brprs) synchronous control register 0 (snyc0) synchronous control register 1 (sync1) mask control register (maskc) dcan macro transceiver ctxd crxd canl canh 293 chapter 17 can controller user?s manual u15251ee4v0ud00 17.6 special function register for can-module the following sfr bits can be accessed with 1-bit instructions. the other sfr registers have to be accessed with 8-bit instructions. table 17-17: sfr definitions register name symbol r/w bit manipulation units after reset 1-bit 8-bit 16-bit can control register canc r/w u u - 01h transmit control register tcr r/w - u - 00h receive message register rmes r - u - 00h redefinition control register redef r/w u u - 00h can error status register canes r/w - u - 00h transmit error counter tec r - u - 00h receive error counter rec r - u - 00h message count register mcnt r - u -c0h bit rate prescaler brprs r/w - u - 00h synchronous control register 0 sync0 r/w - u - 18h synchronous control register 1 sync1 r/w - u -0eh mask control register maskc r/w - u - 00h table 17-18: sfr bit definitions name description bit sofe start of frame enable canc.4 sleep sleep mode canc.2 init initialize canc.0 def redefinition enable redef.7 294 chapter 17 can controller user?s manual u15251ee4v0ud00 17.7 message and buffer configuration notes: 1. contents is undefined, because data resides in normal ram area. 2. this address is an offset to the ram area starting address defined with cadd0/1 in the message count register (mcnt). table 17-19: message and buffer configuration address note 2 register name r/w after reset 00xh transmit buffer 0 r/w note 1 01xh transmit buffer 1 02xh receive message 0 / mask 0 03xh receive message 1 04xh receive message 2 / mask 1 05xh receive message 3 06xh receive message 4 07xh receive message 5 08xh receive message 6 09xh receive message 7 0axh receive message 8 0bxh receive message 9 0cxh receive message 10 0dxh receive message 11 0exh receive message 12 0fxh receive message 13 10xh receive message 14 11xh receive message 15 295 chapter 17 can controller user?s manual u15251ee4v0ud00 17.8 transmit buffer structure the dcan has two independent transmit buffers. the two buffers have a 16-byte data structure for standard and extended frames with th e ability to send up to 8 data by tes per message. the structure of the transmit buffer is similar to the structure of the receive buffers. the cpu can use addresses that are specified as ?unused? in the transmit buffer layout. as well the cpu may use unused id addresses, unused data addresses note , and an unused transmit buffer of the dcan for its own purposes. the con- trol bits, the identification and the message data have to be stored in the message ram area. the transmission control is done by the tcr register. a transmission priority selection allows the cus- tomer to realize an application specific priority se lection. after the priority selection the transmission can be started by setting the txrqn bit (n = 0, 1). in the case that both transmit buffers are used, the transmit priorities can be set. for this purpose the dcan has the txp bit in the tcr register. the application software has to set this priority before the transmission is started. the two transmit buffers supply two independent interrupt lines for an interrupt controller. note: message objects that need less than 8 data byte (dlc < 8) may use the remaining bytes (8 - dlc) for application purposes. 17.9 transmit message format note: this address is a relative offset to the starting address of the transmit buffer. table 17-20: transmit message format name address note bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tcon n0h ide rtr 0 0 dlc3 dlc2 dlc1 dlc0 n1h unused idtx0 n2h id standard part idtx1n3h id standard part 00000 idtx2 n4h id extended part idtx3 n5h id extended part idtx4n6h id extended part000000 n7h unused data0 n8h message data byte 0 data1 n9h message data byte 1 data2 nah message data byte 2 data3 nbh message data byte 3 data4 nch message data byte 4 data5 ndh message data byte 5 data6 neh message data byte 6 data7 nfh message data byte 7 296 chapter 17 can controller user?s manual u15251ee4v0ud00 (1) transmit message definition the memory location labelled tcon includes the information of the rtr bit and the bits of the control field of a data or remote frame. tcon is set with an 1-bit or an 8-bit memory manipulation instruction. reset input sets tcon to an undefined value. figure 17-24: transmit message definition bits remark: the control field describes the format of frame that is generated and its length. the reserved bits of the can protocol are always sent in dominant state (0). note: the data length code selects the number of bytes which have to be transmitted. valid entries for the data length code (dlc) are 0 to 8. if a value greater than 8 is selected, 8 bytes are transmitted in the data frame. the data lengt h code is specified in dlc3 through dlc0. symbol76543210addressafter resetr/w tcon ide rtr 0 0 dlc3 dlc2 dlc1 dlc0 xxx0h undefined r/w ide identifier extension select 0 transmit standard frame message; 11 bit identifier 1 transmit extended frame message; 29 bit identifier rtr remote transmission select 0 transmit data frames 1 transmit remote frames dlc3 dlc2 dlc1 dlc0 data length code selection of transmit message 0000 0 data bytes 0001 1 data bytes 0010 2 data bytes 0011 3 data bytes 0100 4 data bytes 0101 5 data bytes 0110 6 data bytes 0111 7 data bytes 1000 8 data bytes others than above note 297 chapter 17 can controller user?s manual u15251ee4v0ud00 (2) transmit identifier definition these memory locations set the message identifier in the arbitration field of the can protocol. idtx0 to idtx4 register can be set with an 1-bit or an 8-bit memory manipulation instruction. reset input sets idtx0 to idtx4 to an undefined value. figure 17-25: transmit identifier remark: if a standard frame is defined by the ide bit in the tcon byte then idtx0 and idtx1 are used only. idtx2 to idtx4 are free for use by the cpu for application needs. symbol76543210addressafter resetr/w idtx0 id28 id27 id26 id25 id24 id2 3 id22 id21 xxx2h undefined r/w idtx1id20id19id1800000 xxx3h undefined r/w idtx2 id17 id16 id15 id14 id13 id1 2 id11 id10 xxx4h undefined r/w idtx3 id9 id8 id7 id6 id5 id4 id3 id2 xxx5h undefined r/w idtx4id1id0000000 xxx6h undefined r/w 298 chapter 17 can controller user?s manual u15251ee4v0ud00 (3) transmit data definition these memory locations set the transmit message data of the data field in the can frame. data0 to data7 can be set with an 1-bit or an 8-bit memory manipulation instruction. reset input sets data0 to data7 to an undefined value. figure 17-26: transmit data remark: unused data bytes that are not used by the definition in the dlc bits in the tcon byte are free for use by the cpu for application needs. symbol76543210addressafter resetr/w data0 xxx8h undefined r/w data1 xxx9h undefined r/w data2 xxxah undefined r/w data3 xxxbh undefined r/w data4 xxxch undefined r/w data5 xxxdh undefined r/w data6 xxxeh undefined r/w data7 xxxfh undefined r/w 299 chapter 17 can controller user?s manual u15251ee4v0ud00 17.10 receive buffer structure the dcan has up to 16 receive buffers. the number of used buffers is defined by the mcnt register. unused receive buffers can be used as application ram for the cpu. the received data is stored directly in this ram area. the 16 buffers have a 16-byte data structure for standard and extended frames with a capacity of up to 8 data bytes per message. the structure of the receive buffer is similar to the structure of the transmit buffers. the semaphore bits dn and muc enable a secure reception detection and data handling. for the first 8 receive message buffers the successful reception is mirrored by the dn-flags in the rmes register. the receive interrupt request can be enabled or disabled for each used buffer separately. 300 chapter 17 can controller user?s manual u15251ee4v0ud00 17.11 receive message format notes: 1. this address is a relative offset to the start address of the receive buffer. 2. rtr rec is the received value of the rtr message bit when this buffer is used together with a mask function. by using the mask function a successfully received identifier overwrites the bytes idrec0 and idrec1 for standard frame format and idrec0 to idrec4 for extended frame format. for the rtr rec bit exist two modes: rtr bit in the mcon byte of the dedicated mask is set to 0. in this case rtr rec will always be written to 0 together with the update of the idn bits in idrec1. the received frame type (data or remote) is defined by the rtr bit in idcon of the buffer. rtr bit in the mcon byte of the dedicated mask is set to 1 (data and remote frames are accepted). in this case the rtr bit in idcon has no meaning. the received mes- sage type passed the mask is shown in rtr rec . if a buffer is not assigned to a mask function (mask 1, mask 2 or global mask) the bytes idrec0 to idrec4 are only read for co mparing. during init ialization the rtr rec should be defined to 0. table 17-21: receive message format name address note 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 idcon n0h 0 0 0 0 0 eni rtr ide dstat n1h dn muc r1 r0 dlc idrec0 n2h id standard part idrec1 n3h id standard part 0 0 0 0 rtr rec note 2 idrec2 n4h id extended part idrec3 n5h id extended part idrec4 n6h id extended part00000 0 n7h unused data0 n8h message data byte 0 data1 n9h message data byte 1 data2 nah message data byte 2 data3 nbh message data byte 3 data4 nch message data byte 4 data5 ndh message data byte 5 data6 neh message data byte 6 data7 nfh message data byte 7 301 chapter 17 can controller user?s manual u15251ee4v0ud00 (1) receive control bits definition the memory location labelled idcon defines the kind of frame (data or remote frame with stand- ard or extended format) that is monitored for the associated buffer. notification by the receive inter- rupt upon successful reception can be selected for each receive buffer separately. idcon can be set with an 1-bit or an 8-bit memory manipulation instruction. reset input sets idcon to an undefined value. figure 17-27: control bits for receive identifier the control bits define the type of message that is transferred in the associated buffer if this type of message appears on the bus. this byte will never be written by the dcan. only the host cpu can change this byte. note: the user has to define with the eni bit if he wants to set a receive interrupt request when new data is received in this buffer. symbol76543210addressafter resetr/w idcon00000enirtride xxx0h undefined r/w ide identifier extension select 0 receive standard frame message; 11-bit identifier 1 receive extended frame message; 29-bit identifier rtr remote transmission select 0 receive data frames 1 receive remote frames eni enable interrupt on receive note 0 no interrupt generated 1 generate receive interrupt after reception of valid message 302 chapter 17 can controller user?s manual u15251ee4v0ud00 (2) receive status bits definition the memory location labelled dstat sets the receive status bits of the arbitration field of the can protocol. dstat can be set with an 1-bit or an 8-bit memory manipulation instruction. reset input sets dstat to an undefined value. figure 17-28: receive status bits (1/2) the receive status reflects the current status of a message. it signals whether new data is stored or if the dcan currently transfers data into this buffer. in addition the data length of the last transferred data and the reserved bits of the protocol are shown. the dcan-module sets dn twice. at first when it starts storing a message from the shadow buffer into the receive buffer and secondly when it finished the operation. the cpu needs to clear this bit, to signal by itself that it has read the data. during initialization of the receive buffers the dn-bit should also be cleared. otherwise the cpu gets no information on an update of the buffer after a successful reception. the dcan-module sets muc when it starts transferri ng a message into the buffer and clears the muc bit when the transfer is finished. symbol76543210addressafter resetr/w dstat dn muc r1 r0 dlc3 dlc2 dlc1 dlc0 xxx1h undefined r/w dn data new 0 no change in data 1 data changed muc memory update 0 can does not access data part 1 can is transferring new data to message buffer r1 reserved bit 1 0 reserved bit 1 of received message was ?0? 1 reserved bit 1 of received message was ?1? r0 reserved bit 0 0 reserved bit 0 of received message was ?0? 1 reserved bit 0 of received message was ?1? 303 chapter 17 can controller user?s manual u15251ee4v0ud00 figure 17-28: receive status bits (2/2) dstat is written by the dcan two times during message storage: at the first access to this buffer dn = 1, muc = 1, reserved bits and dlc are written. at the last access to this buffer dn = 1, muc = 0, reserved bits and dlc are written. note: valid entries for the data length code are 0 to 8. if a value higher than 8 is received, 8 bytes are stored in the message buffer frame together with the data length code received in the dlc of the message. dlc3 dlc2 dlc1 dlc0 data length code selection of receive message 0 0 0 0 0 data bytes 0 0 0 1 1 data bytes 0 0 1 0 2 data bytes 0 0 1 1 3 data bytes 0 1 0 0 4 data bytes 0 1 0 1 5 data bytes 0 1 1 0 6 data bytes 0 1 1 1 7 data bytes 1 0 0 0 8 data bytes others than above note 304 chapter 17 can controller user?s manual u15251ee4v0ud00 (3) receive identifier definition these memory locations define the receive identifier of the arbitration field of the can protocol. idrec0 to idrec4 can be set with an 1-bit or an 8-bit memory manipulation instruction. reset input sets idrec0 to idrec4 to an undefined value. figure 17-29: receive identifier the identifier of the receive message has to be defined during the initialization of the dcan. the dcan uses this data for the comparison with the identifiers received on the can bus. for normal message buffers without mask function this data is only read by the dcan for comparison. in combina- tion with a mask function this data is overwritten by the received id that has passed the mask. the identifier of the receive messages should not be changed without being in the initialization phase or setting the receive buffer to redefinition in the rdef register, because the change of the contents can happen at the same time when the dcan uses t he data for comparison. this can cause inconsistent data stored in this buffer and also the id-part can be falsified in case of using mask function. remarks: 1. the unused parts of the identifier (idrec1 bit 4 - 0 always and idrec4 bit 5 - 0 in case of extended frame reception) may be written by the dcan to ?0?. they are not released for other use by the cpu. 2. rtr rec is the received value of the rtr message bit when this buffer is used together with a mask function. by using the mask function a successfully received identifier overwrites the idrec0 and idrec1 registers for standard frame format and the idrec0 to idrec4 registers for extended frame format. for the rtr rec bit exists two modes: rtr bit in the mcon register of the dedicated mask is set to ?0?. in this case rtr rec bit will always be written to ?0? toget her with the update of the idn bits (n = 18 to 20) in idrec1. the received frame type (data or remote) is defined by the rtr bit in idcon of the buffer. rtr bit in the mcon register of the dedicated mask is set to ?1? (data and remote frames are accepted). in this case the rtr bit in idcon register has no meaning. the received message type passed the mask is shown in rtr rec bit. if a buffer is not dedicated to a mask f unction (mask 1, mask 2 or global mask) the idrec0 to idrec4 registers are only read for comparing. all receive identifiers should be defined to ?0? before the application sets up its specific values. symbol76543210addressafter resetr/w idrec0 id28 id27 id26 id25 id24 id23 id22 id21 xxx2h undefined r/w idrec1id20id19id180000 rtr rec xxx3h undefined r/w idrec2 id17 id16 id15 id14 id13 id12 id11 id10 xxx4h undefined r/w idrec3 id9 id8 id7 id6 id5 id4 id3 id2 xxx5h undefined r/w idrec4id1id0000000 xxx6h undefined r/w 305 chapter 17 can controller user?s manual u15251ee4v0ud00 (4) receive message data part these memory locations set the receive message data part of the can protocol. data0 to data7 can be set with an 1-bit or an 8-bit memory manipulation instruction. reset input sets data0 to data7 to an undefined value. figure 17-30: receive data the dcan stores received data bytes in this memory area. only those data bytes which are actually received and match with the identifier are stored in the receive buffer memory area. if the dlc is less than eight, the dcan will not writ e additional bytes exceeding the dlc value up to eight. the dcan stores a maximum of 8 bytes (according to the can protocol rules) even when the received dlc is greater than eight. symbol76543210addressafter resetr/w data0 xxx8h undefined r/w data1 xxx9h undefined r/w data2 xxxah undefined r/w data3 xxxbh undefined r/w data4 xxxch undefined r/w data5 xxxdh undefined r/w data6 xxxeh undefined r/w data7 xxxfh undefined r/w 306 chapter 17 can controller user?s manual u15251ee4v0ud00 17.12 mask function receive message buffer 0 and buffer 2 can be switched for masked operation with the mask control register (maskc). in this case the message does not hold message identifier and data of the frame. instead, it holds identifier and rtr mask information for masked compare operations for the next higher message buffer number. in case the global mask is selected, it keeps mask information for all higher message buffer numbers. a mask does not store any information about identifier length. therefore the same mask can be used for both types of frames (standard and extended) during global mask operation. all unused bytes can be used by the cpu for application needs. (1) identifier compare with mask the identifier compare with mask provides the possibility to exclu de some bits from the compari- son process. that means each bit is ignored wh en the corresponding bit in the mask definition is set to one. the setup of the mask control register (maskc) defines which receive buffer is used as a mask and which receive buffer uses which mask for comparison. the mask does not include any information about the identifier type to be masked. this has to be defined within the dedicated receive buffer. therefore a global mask can serve for standard receive buffers at the same time as for extended receive buffer. table 17-22: mask function name address bit 7 bit 6 bit 5 b it 4 bit 3 bit 2 bit 1 bit 0 mcon n0h rtr n1h unused mrec0 n2h id standard part mrec1 n3h id standard part 0 0 0 0 0 mrec2 n4h id extended part mrec3 n5h id extended part mrec4 n6h id extended part 000000 n7h unused n8h unused n9h unused nah unused nbh unused nch unused ndh unused neh unused nfh unused 307 chapter 17 can controller user?s manual u15251ee4v0ud00 figure 17-31: identifier compare with mask this function implements the so called basic-can behaviour. in this case the type of identifier is fixed to standard or extended by the setup of the ide bit in the receive buffer. the comparison of the rtr bit can also be masked. it is possible to receive data and remote frames on the same masked receive buffer. the following information is stored in the receive buffer: identifier (11 or 29 bit as defined by ide bit) remote bit (rtr rec ) if both frames types (data or remote) can be received by this buffer reserved bits data length code (dlc) data bytes as defined by dlc caution: all writes into the dcan memory are by te accesses. unused bi ts in the same byte will be written zero. unused bytes will not be written and are free for application use by the cpu. received identifier mask stored in receive buffer 0 or 2 identifier stored in receive buffer compare bit by bit disable compare for masked bits store on equal 308 chapter 17 can controller user?s manual u15251ee4v0ud00 (2) mask identifier control register (mcon) the memory location labelled mcon sets the mask identifier control bit of the can protocol. mcon can be set with an 1-bit or an 8-bit memory manipulation instruction. reset input sets mcon to an undefined value. figure 17-32: control bits for mask identifier notes: 1. for rtr = 0 the received frame type (data or remote) is defined by the rtr bit in idcon of the dedicated buffer. in this case rtr rec will always be written to ?0? togeth er with the update of the idn bits (n = 18 to 20) in idrec1. 2. in case rtr in mcon is set to ?1?, rtr bit in idcon of the dedicated receive buffer has no meaning. the received message type passed the mask is shown in the rtr rec bit. symbol76543210addressafter resetr/w mcon000000rtr0 xxx0h undefined r/w rtr remote transmission select 0 check rtr bit of received message note 1 1 receive message independent from rtr bit note 2 309 chapter 17 can controller user?s manual u15251ee4v0ud00 (3) mask identifier definition these memory locations set the mask identifier definition of the dcan. mrec0 to mrec4 can be set with an 1-bit or an 8-bit memory manipulation instruction. reset input sets mrec0 to mrec4 to an undefined value. figure 17-33: mask identifier symbol76543210addressafter resetr/w mrec0 mid28 mid27 mid26 mid25 mid24 mi d23 mid22 mid21 xxx2h undefined r/w mrec1mid20mid19mid1800000 xxx3h undefined r/w mrec2 mid17 mid16 mid15 mid14 mid13 mi d12 mid11 mid10 xxx4h undefined r/w mrec3 mid9 mid8 mid7 mid6 mid5 mid 4 mid3 mid2 xxx5h undefined r/w mrec4mid1mid0000000 xxx6h undefined r/w midn mask identifier bit (n = 0...28) 0 check idn bit in idrec0 through idrec4 of received message 1 receive message independent from idn bit 310 chapter 17 can controller user?s manual u15251ee4v0ud00 17.13 operation of the can controller 17.13.1 can contro l register (canc) the operational modes are controlled via the can control register canc. canc can be set with an 1-bit or an 8-bit memory manipulation instruction. reset input sets canc to 01h. figure 17-34: can control register (1/2) canc.5 has always to be written as 0. the init is the request bit to control the dcan. init starts and stops the can protocol activities. due to bus activities disabling the dcan is not allowe d any time. therefore changing the init bit must not have an immediate effect to the can protocol activities. setting the init bit is a request only. the initstat bit in the canes register reflects if the request has been granted. the registers mcnt, sync0, sync1, and maskc are write protected while init is cleared inde pendently of initstat. any write to these registers when init is set and the initialisation mode is not confirmed by the initstat bit can have unexpected behaviour to the can bus. symbol 7 6 5 <4> 3 <2> 1 <0> address after reset canc rxf txf 0 sofe sofsel sleep stop init ffb0h 01h r r r r/w r/w r/w r/w r/w init request status for operational modes 0 normal operation 1 initialization mode stop stop mode selection 0 normal sleep operation / sleep mode is released when a transition on the can bus is detected 1 stop operation / sleep mode is cancelled only by cpu access. no wake up from can bus sleep sleep/stop request for can protocol 0 normal operation 1 can protocol goes to sleep or stop mode depending on stop bit 311 chapter 17 can controller user?s manual u15251ee4v0ud00 figure 17-34: can control register (2/2) the clock supply to the dcan is switched off during initialization, dcan sleep, and dcan stop mode. all modes are only accepted while can protocol is in idle state, whereby the crxd pin must be reces- sive (= high level). a sleep or st op request out of idle state is rejected and the wake bit in canes is set. dcan sleep and dcan stop mode can be req uested in the same manner. the only difference is that the dcan stop mode prevents the wake up by can bus activity. caution: the dcan sleep or dcan st op mode can not be requested as long as the wake bit in canes is set. the dcan sleep mode is cancelled under following conditions: a) cpu clears the sleep bit. b) any transition while idle state on can bus (stop = 0). c) cpu sets sleep, but can protocol is active due to bus activity. the wake bit in canes is se t under condition b) and c). figure 17-35: dcan support the generation of an sofout signal can be used fo r time measurements and for global time base syn- chronization of different can nodes as a prerequisite for time triggered communication. sofsel start of frame output function select 0 last bit of eof is used to generate the time stamp 1 sof is used to generate the time stamp sofe start of frame enable 0 sofout does not change 1 sofout toggles depending on the selected mode 16 bit timer frc capture register sofc dcan sof data crc eof mux t-ff sofsel sofe receive buffer 4 clear tq last bit of eof sofout 312 chapter 17 can controller user?s manual u15251ee4v0ud00 sofc is located in the synchronization register sync1. reset and setting of the init bit of canc register clears the sofout to 0. the txf and rxf bits of canc register show the present status of the dcan to the bus. if both bits are cleared, the bus is in idle state. rxf and txf bits are read-only bits. during initialization mode both bits do not reflect the bus status. note: transmission is active until intermission is completed. table 17-23: possible setup of the sofout function sofsel sofc sofe sofout function x x 0 time stamp function disabled 0 x 1 toggles with each eof 101 toggles with each start of frame on the can bus 111 toggles with each start of frame on the can bus. clears sofe bit when dcan starts to store a message in receive buffer 4 table 17-24: transmission / reception flag txf transmission flag 0 no transmission 1 transmission active on can bus note rxf reception flag 0 no data on the can bus 1 reception active on the can bus 313 chapter 17 can controller user?s manual u15251ee4v0ud00 figure 17-36: time stamp function figure 17-37: sofout toggle function figure 17-38: global time system function valid message other valid or invalid message valid message int object n int object n enable sof edge for capture edge for capture sof sof sof any valid or invalid message enable sof edge for capture sof sof sof any valid or invalid message any valid or invalid message edge for capture edge for capture other valid or invalid message int object n enable sof edge for capture sof sof sof other valid or invalid message valid sync. message buffer 4 edge for capture disable sof 314 chapter 17 can controller user?s manual u15251ee4v0ud00 17.13.2 dcan error status register (canes) this register shows the status of the dcan. canes has to be set with an 8-bit memory manipulation instruction. reset input sets canes to 00h. the reset sets the init -bit in canc register, therefore canes will be read as 08h after reset release. figure 17-39: can error status register (1/3) remark: boff, recs, tecs and initstate are read only bits. caution: don?t use bit operations on this sfr. the valid, wake and over bits have a special behavior during cpu write operations: writing a ?0? to them do not change them. writing an ?1? clears the associated bit. this avoids any timing conflicts between cpu access and internal activities. an internal set condition of a bit overrides a cpu clear request at the same time. boff is cleared after receiving 128 x 11 bits recess ive state (bus idle) or by issuing a hard dcan reset with the tlres bit in the mcntn register note . an interrupt is generated when the boff bit changes its value. recs is updated after each reception. an interrupt is generated when recs changes its value. note: issuing tlres bit may violate the minimum recovery time as defined in iso-11898. symbol7654 3 210address after reset canes boff recs tecs 0 initstate valid wake over ffb4h 00h rrrr r r/wr/wr/w boff bus off flag 0 transmission error counter d 255 1 transmission error counter > 255 recs reception error counter status 0 reception error counter < 96 1 reception error counter t 96 / warning level for error passive reached 315 chapter 17 can controller user?s manual u15251ee4v0ud00 figure 17-39: can error status register (2/3) tecs is updated after each reception. an interrupt is generated when tecs changes its value. initstate changes with a delay to the init bit in canc register. the delay depends on the current bus activity and the time to set all internal activities to inactive state. this time can be several bit times long. while boff bit is set, a request to go into the initialization mode by setting the init bit is ignored. in this case the initstate bit will not be set until the bus-off state is left. this bit shows valid protocol activities independent from the message definitions and the rxonly bit setting in sync1n register. valid is updated after each re ception. the valid bit will be set at the end of the frame when a complete protocol without errors has been detected. cautions: 1. the valid bit is cleared if cpu writes an ?1? to it, or when the init bit in canc register is set. 2. writing a ?0? to the valid bit has no influence. tecs transmission error counter status 0 transmission error counter < 96 1 transmission error counter t 96 / warning level for error passive reached initstate operational status of the dcan 0 can is in normal operation 1 can is stopped and ready to accept new configuration data valid valid protocol activity detected 0 no valid message detected by the can protocol 1 error free message reception from can bus 316 chapter 17 can controller user?s manual u15251ee4v0ud00 figure 17-39: can error status register (3/3) this bit is set and an error interrupt is generated under the following circumstances: a) a can bus activity occurs during dcan sleep mode. b) any attempt to set the sleep bit in the can cont rol register during rece ive or transmit opera- tion will immediately set the wake bit. the cpu must clear this bit after recognition in order to receive further error interrupts, because the error interrupt line is kept active as long as this bit is set. cautions: 1. the wake bit is cleared to ?0? if cp u writes an ?1? to it, or when the init bit in canc register is set. 2. writing a ?0? to the wake bit has no influence. the overrun condition is set whenever the can can not perform all ram accesses that are necessary for comparing and storing received data or fetching transmitted data. typically, the overrun condition is encountered when the frequency for the macro is too low compared to the programmed baud rate. an error interrupt is generated at the same time. the dcan interface will work properly (i. e. no ov errun condition will occur) with the following settings: the dcan clock as defined with the prm bits in the brprs register is set to a minimum of 16 times of the can baudrate and the selected cpu clock (defined in the pcc register) is set to a minimum of 16 times of the baudrate. possible reasons for an overrun condition are: too many messages are defined. dma access to ram area is too slow compared to the can baudrate. the possible reactions of the dcan differ depending on the situation, when the overrun occurs. wake wake up condition 0 normal operation 1 sleep mode has been cancelled or sleep/stop mode request was not granted over overrun condition 0 normal operation 1 overrun occurred during access to ram 317 chapter 17 can controller user?s manual u15251ee4v0ud00 17.13.3 can transmit error counter (tec) this register shows the transmit error counter. tec register can be read with an 8-bit memory manipulation instruction. reset input sets tec to 00h. figure 17-40: transmit error counter the transmit error counter reflects the status of the er ror counter for transmission errors as it is defined in the can protocol according iso 11898. 17.13.4 can receive error counter (rec) this register shows th e receive error counter. rec can be read with an 8-bit memory manipulation instruction. reset input sets rec to 00h. figure 17-41: receive error counter the receive error counter reflects the status of the error counter for reception errors as it is defined in the can protocol according iso 11898. table 17-25: possible reactions of the dcan overrun situation when detected dcan behavior cannot get transmit data. next data byte request from protocol. immediate during the frame. the frame itself conforms to the can specification, but it s content is faulty. corrupted data or id in the frame. txrqx bit (x = 0, 1) is not cleared. dcan will retransmit the correct frame after synchronization to the bus. cannot store receive data. data storage is ongoing during the six bit of the next frame. data in ram is inconsistent. no receive flags. dn and muc bit may be set in message. cannot get data for id comparison id compare is ongoing during six bits of next frame. message is not received and its data is lost. symbol76543210address after reset tec tec7 tec6 tec5 tec4 tec3 tec2 tec1 tec0 ffb5h 00h rrrrrrrr symbol76543210address after reset rec rec7 rec6 rec5 rec4 rec3 rec2 rec1 rec0 ffb6h 00h rrrrrrrr 318 chapter 17 can controller user?s manual u15251ee4v0ud00 17.13.5 message count register (mcnt) this register sets the number of receive message buffers and allocates the ram area of the receive message buffers, which are handled by the dcan-module. mcnt can be read with an 8-bit memory manipulation instruction. reset input sets mcnt to c0h. figure 17-42: message count register (mcnt) (1/2) this register is readable at any time. write is only permitted when the can is in initialization mode. symbol76543210addressafter reset mcnt cadd1 cadd0 tlres mcnt4 mcnt3 mcnt2 mcnt1 mcnt0 ffb7h c0h r/w r/w r/w r/w r/w r/w r/w r/w mcnt4 mcnt3 mcnt2 mcnt1 mcnt0 receive message count 0 0 0 0 0 setting prohibited 000011 receive buffer 000102 receive buffer 000113 receive buffer 001004 receive buffer 001015 receive buffer 001106 receive buffer 001117 receive buffer 010008 receive buffer 010019 receive buffer 0 1 0 1 0 10 receive buffer 0 1 0 1 1 11 receive buffer 0 1 1 0 0 12 receive buffer 0 1 1 0 1 13 receive buffer 0 1 1 1 0 14 receive buffer 0 1 1 1 1 15 receive buffer 1 0 0 0 0 16 receive buffer 1xxxx setting prohibited, will be automatically changed to 16 319 chapter 17 can controller user?s manual u15251ee4v0ud00 figure 17-42: message count register (mcnt) (2/2) cautions: 1. issuing tlres bit may violate th e minimum recovery ti me as defined in iso- 11898. 2. if no receive buffer is desired, define one receive buffer and disable this buffer with the redef function. tlres reset function for can protocol machine 0 no reset is issued 1 reset of can protocol machine is issued if dcan is in bus off state, dcan will enter init state (canc.0 = 1 && canes.3 = 1) cadd1 cadd0 dcan address definition 00 setting prohibited 01 10 1 1 f600h to f7dfh (reset value) 320 chapter 17 can controller user?s manual u15251ee4v0ud00 17.14 baudrate generation (1) bit rate prescaler register (brprs) this register sets the clock for the dcan (interna l dcan clock) and the number of clocks per time quantum (tq). brprs can be set with an 8-bit memory manipulation instruction. reset input sets brprs to 3fh. figure 17-43: bit rate prescaler (1/2) the prmn (n = 0, 1) bits define the clock source for the dcan operation. the prm selector defines the input clock to the dcan macro and influences therefore all dcan activities. writing to the brprs register is only allowed during initialization mode. any writ e to this register when init bit is set in canc register and the initialization mode is not confirmed by the initstate bit of canes register can cause unexpected behaviour to the can bus. the brprsn bits (n = 0 to 5) define the number of dcan clocks applied for one tq. for brprsn (n = 0 to 5) two modes are available depending on the tlmode bit in the sync1 register. symbol76543210addressafter reset brprs prm1 prm0 brprs5 brprs4 brprs3 brprs2 brprs1 brprs0 ffb8h 3fh r/w r/w r/w r/w r/w r/w r/w r/w prm1 prm0 input clock selector for dcan clock 00 f x is input for dcan 01 f x /2 is input for dcan 10 f x /4 is input for dcan 1 1 cclk is input for dcan 321 chapter 17 can controller user?s manual u15251ee4v0ud00 figure 17-43: bit rate prescaler (2/2) setting of brprsn (n = 5 to 0) for tlmode = 0: note: the bit rate prescaler value repr esents the dcan clocks per tq. setting of brprsn (n = 7 to 0) for tlmode = 1: note: when using this setting the user needs to assure that phase segment 2 consists of at least 3 tq. phase segment 2 is given by the difference of dbt - spt each measured in units of tq. brprs7 and brprs6 are loca ted in the maskc register. brprs5 brprs4 brprs3 brprs2 brprs1 brprs0 bit rate prescaler note 000000 2 000001 4 000010 6 000011 8 ...... . ......2 x brprsn[5-0] + 2 ...... . 111010 118 111011 120 111100 122 111101 124 111110 126 111111 128 brprs7 brprs6 brprs5 brprs4 brprs3 brpr s2 brprs1 brprs0 bit rate prescaler 00000000 1 note 00000001 2 00000010 3 00000011 4 ...... . . . . . . . brprsn[7-0] +1 ...... . 11111010 123 11111011 124 11111100 125 11111101 126 11111110 127 11111111 128 322 chapter 17 can controller user?s manual u15251ee4v0ud00 (2) synchronization control registers (sync0 and sync1) these registers define the can bit timing. they define the length of one data bit on the can bus, the position of the sample point during the bit timing, and the synchronization jump width. the range of resynchronization can be adapted to different can bus speeds or network characteris- tics. additionally, some modes related to the baud rate can be selected in sync1 register. sync0 and sync1 can be read or written with an 8-bit memory manipulation instruction. reset input sets sync0 to 18h. reset input sets sync1 to 0eh. figure 17-44: synchronization control registers 0 and 1 (1/2) the length of a data bit time is programmable via dbt[4-0]. symbol7 65 4 3210addressafter resetr/w sync0 spt2 spt1 spt0 dbt4 dbt3 dbt2 dbt1 dbt0 ffb9h 18h r/w symbol7 65 4 3210addressafter resetr/w sync1 tlmode sofc samp 0 sjw1 sjw0 spt4 spt3 ffbah 0eh r/w dbt4 dbt3 dbt2 dbt1 dbt0 data bit time other than under setting prohibited 001118 x tq 010009 x tq 0100110 x tq 0101011 x tq 0101112 x tq 0110013 x tq 0110114 x tq 0111015 x tq 0111116 x tq 1000017 x tq 1000118 x tq 1001019 x tq 1001120 x tq 1010021 x tq 1010122 x tq 1011023 x tq 1011124 x tq 1100025 x tq other than above setting prohibited 323 chapter 17 can controller user?s manual u15251ee4v0ud00 figure 17-44: synchronization control registers 0 and 1 (2/2) the position of the sample point within the bit timing is defined by spt0n through spt4n. note: the user needs to assure that phase segment 2 (tseg2) consists of at least 3 tq when using this setting. phase segment 2 is given by the di fference of dbt - spt each measured in units of tq. sjw0 and sjw1 define the synchronization jump width as specified in iso 11898. spt4 spt3 spt2 spt1 spt0 s ample point position other than under setting prohibited 000012 x tq 000103 x tq 000114 x tq 001005 x tq 001016 x tq 001107 x tq 001118 x tq 010009 x tq 0100110 x tq 0101011 x tq 0101112 x tq 0110013 x tq 0110114 x tq 0111015 x tq 0111116 x tq 1000017 x tq other than above setting prohibited tlmode resolution of bit rate prescaler 0 1 unit of brprs[5-0] in brprs regi ster equals 2 dcan clocks, brprs[7-6] in maskc register are disabled (c ompatible to older macro versions) 1 1 unit of brprs[7-0] in brprs and maskc register equals 2 dcan clocks, brprs[7-6] in maskc register are enabled note sjw1 sjw0 synchronisation jump width 00 1 x tq 01 2 x tq 10 3 x tq 11 4 x tq 324 chapter 17 can controller user?s manual u15251ee4v0ud00 limits on defining the bit timing the sample point position needs to be programmed between 3tq note and 17tq, which equals a register value of 2 d sptxn d 16 (n = 0, 1; x = 4 to 0). the number of tq per bit is restricted to the range from 8tq to 25tq, which equals a register value of 7 d dbtxn d 24 (n = 0, 1; x = 4 to 0). the length of phase segment 2 (tseg2) in tq is given by the difference of tq per bit (dbtxn) and the sample point position (sptxn). converted to register values the following condition applies: 2 d dbtxn - sptxn d 8 (n = 0, 1; x = 4 to 0). the number of tq allocated for soft synchronization must not exceed the number of tq for phase segment 2, but sjwyn may have as many tq as phase segment 2: sjwyn d dbtxn - sptxn - 1 (n = 0, 1; x = 4 to 0; y = 0, 1). note: sample point positions of 3 tq or 4 tq are for test purposes only. for the minimum number of tq per bit time, 8tq, the minimum sample point position is 5 tq. example : at first, calculate the overall prescaler value: 16 can be split as 1 x 16 or 2 x 8. other factors can not be mapped to the registers. only 8 and 16 are valid values for tq per bit. therefore the overall prescaler value realized by brprsn is 2 or 1 respectively. with tlmode = 0 the following register settings apply: system clock: fx 8 mhz can parameter: baud rate 500 kbaud sample point 75% sjw 25% register value description bit fields brprsn = 00h clock selector = fx prmn = 00b brprsx = 000000b sync0n = a7h can bit in tq = 8 dbtx = 00111b 7 < (fx/baudrate/bit rate prescaler) < 25] sync1n = 0zzz0100b sample point 75% = 6 tq sptx = 00101b sjw 25% = 2 tq sjwy = 01b 1 tq equals 2 clocks & brprs6, 7 are disabled tlmode = 0 z depends on the setting of: - number of sampling points - receive only function - use of time stamp or global time system f x baudrate ------------------------ 8 mhz 500 kbaud ---------------------------- - 16 = = 325 chapter 17 can controller user?s manual u15251ee4v0ud00 with tlmode = 1 the following register settings apply: the valid bit in canes reports if the dc an interface receives any valid message. samp defines the number of sample points per bit as specified in the iso-11898. sofc works in conjunction with the sofe and sofsel bits in the can control register canc. for detailed information please refer to the bit description of that sfr register and the time function mode. caution: cpu can read sync0/sync1 register at any time. writing to the sync0/sync1 registers is only allowed during initialization mode. any write to this register when init is set and the initialization mode is not confirmed by the initstate bit can have unexpected behavior to the can bus. register values description bit fields brprsn = 00h clock selector = fx prmn = 00b maskcn = 00xx xxxxb brprsn = 0000 0000b sync0n = 6fh can bit in tq = 16 dbtn = 01111b 7 < (fx/baudrate/bit rate prescaler) < 25] sync1n = 1zzz 1101b sample point 75% = 12 tq: sptn = 01011b sjw 25% = 4 tq sjwn = 11b 1 tq equals 1 clock, brprs 6, 7 are enabled tlmode = 1 z depends on the setting of: - number of sampling points - receive only function - use of time stamp or global time system samp bit sampling 0 sample receive data one time at receive point 1 sample receive data three times and take majority decision at sample point sofc start of frame control 0 sofe bit is independent from can bus activities 1 sofe bit will be cleared when a message for receive message 4 is received and sof mode is selected 326 chapter 17 can controller user?s manual u15251ee4v0ud00 17.15 function control 17.15.1 transmit control (1) transmit control register (tcr) this register controls the transmission of the dcan-module. the transmit control register (tcr) provides complete control over the two transmit buffers and their status. it is possible to request and abort transmission of both buffers independently. tcr can be set with an 8-bit memory manipulation instruction. reset input sets tcr to 00h. figure 17-45: transmit control register (1/2) caution: don't use bit operations on this register . also logical operati ons (read-modify-write) via software may lead to unexpected transmissions. initiating a transmit request for buffer 1 while txrq0 is already set, is simply achieved by writing 02h or 82h. the status of the bits for buffer 0 is not affected by this write operation. the user defines which buffer has to be send first in the case of both request bits are set. if only one buffer is requested by the txrqn bits (n = 0, 1) bits, txp bit has no influence. txcn (n = 0, 1) shows the status of the first transmission. it is updated when txrqn (n = 0, 1) is cleared. the txan bits (n = 0, 1) allow to free a transmit buffer with a pending transmit request. setting the txan bit (n = 0, 1) by the cpu requests the dcan to empty its buffer by clearing the respective txrqn bit (n = 0, 1). symbol76543210addressafter reset tcr txp 0 txc1 txc0 txa1 txa0 txrq1 txrq0 ffb1h 00h r/w r r r r/w r/w r/w r/w txp transmission priority 0 buffer 0 has priority over buffer 1 1 buffer 1 has priority over buffer 0 txan transmission abort flag 0 write: normal operation read: no abort pending 1 write: aborts current transmission request for this buffer n read: abort is pending txcn transmission complete flag 0 transmit was aborted / no data sent 1 transmit was complete / abort had no effect 327 chapter 17 can controller user?s manual u15251ee4v0ud00 figure 17-45: transmit control register (2/2) the txan bits (n = 0, 1) have a dual function: 1. the cpu can request an abort by writing an ?1? into the bit. 2. the dcan signals whether such an request is still pending. the bit is cleared at the same time when the txrqn bit (n = 0, 1) is cleared. the abort process does not affect any rules of th e can protocol. a frame already started will continue to its end. an abort operation can cause different results dependent on the time it is issued. d) when an abort request is recognized by the dcan before the start of the arbitration for transmit, the txcn bit (n = 0, 1) is reset showing that the buffer was not send to other nodes. e) when the abort request is recognized during the arbitration and the arbitration is lost afterwards, the txcn bit (n = 0, 1) is reset showing that the buffer was not send to other nodes. f) when the abort request is recognized during frame transmission and the transmission ends with an error afterwards, the txcn bit (n = 0, 1) is reset showing that the buffer was not send to other nodes. g) when the abort request is recognized during th e frame transmission and transmission ends with- out error. the txcn bit (n = 0, 1) is set showing a successful transfer of the data. i.e the abort request was not issued. in all cases the txrqn bit and the t xan bit (n = 0, 1) bit will be clea red at the end of the abort opera- tion, when the transmit buffer is available again. cautions: 1. the bits are cleared when the init bit in canc register is set. 2. writing a 0 to txan (n = 0, 1) bit has no influence 3. do not perform read-modify-write operations on tcr. the txcn bit (n = 0, 1) are updated at the end of every frame transmission or abort. the transmit request bits are checked by the dcan immediately before the frame is started. the order in which the txrqn bit (n = 0, 1) will be set does not matter as long as the fi rst requested frame is not started on the bus. the txrqn bit (n = 0, 1) have dual function: 1. request the transmission of a transmit buffer. 2. inform the cpu whether a buffer is available or if it is still occupied by a former transmit request. setting the transmission request bit requests the dcan to sent the buffer contents onto the bus. the dcan clears the bit after completion of the transmission. completion is either a normal transfer without error or an abort request. txrqn transmission request flag 0 write: no influence read: transmit buffer is free 1 write: request transmission for buffer n read: transmit buffer is occupied by former transmit request 328 chapter 17 can controller user?s manual u15251ee4v0ud00 an error during the transmission does not infl uence the transmit request status. the dcan will auto- matically retry the transfer. cautions: 1. the bits are cleared when the init bit in canc is set. a transmission already started will be finished but not retransmitted in case of an error. 2. writing a ?0? to txrq0 bit has no influence. 3. do not use bit operations on this register. 4. do not change data in transmit buffer when the corresponding txrq bit is set. 17.15.2 receive control the receive message register mirrors the current status of the first 8 receive buffers. each buffer has one status bit in this register. this bit is always set when a new message is completely stored out of the shadow buffer into the associated buffer. the cpu can easily find the last received message during receive interrupt handling. the bits in this register always correspond to the dn bit in the data buffers. they are cleared when the cpu clears the dn bit in the data buffer. the register itself is read only. (1) receive message register (rmes) this register shows receptions of messages of the dcan-module. more than one bit set is possi- ble. rmes can be read with an 1-bit or an 8-bit memory manipulation instruction. reset input sets rmes to 00h. figure 17-46: receive message register this register is read only and it is cleared when the init bit in canc register is set. dn0 bit has no meaning when receive buffer 0 is configured for mask operation in the mask control register. dn2 bit has no meaning when receive buffer 2 is configured for mask operation in the mask control register. symbol76543210addressafter reset rmes dn7 dn6 dn5 dn4 dn3 dn2 dn1 dn0 ffb2h 00h rrrrrrrr dn data new bit for message n (n = 0...7) 0 no message received on message n or cpu has cleared dn bit in message n 1 data received in message n that was not acknowledged by the cpu 329 chapter 17 can controller user?s manual u15251ee4v0ud00 17.15.3 mask control the mask control register defines whether the dcan compares all identifier bits or if some bits are not used for comparison. this functionality is provided by the use of the mask information. the mask infor- mation defines for each bit of the identifier whether it is used for comparison or not. the dcan uses a receive buffer for this information, when it is enabled by the mask control register. in this case this buffer is not used for normal message storage. unused bytes can be used for application needs. (1) mask control register (maskc) this register controls the mask function applied to any received message. maskc can be written with an 8-bit memory manipulation instruction. reset input sets maskc to 00h. figure 17-47: mask control register (1/2) note: brprs[7 - 6] are only enable if tlmode is set to 1. caution: this register is readable at any time. writing to the maskc register is only allowed during initialization mode. any write to this register when init bit is set and the initialization mode is not confirmed by the initstate bit can have unexpected behavior to the can bus. symbol 7 note 6 note 543210addressafter reset maskc brprs7 brprs6 ssht al 0 global msk1 msk0 ffbbh 00h r/w r/w r/w r/w r r/w r/w r/w msk0 mask 0 enable 0 receive buffer 0 and 1 in normal operation 1 receive buffer 0 is mask for buffer 1 msk1 mask 1 enable 0 receive buffer 2 and 3 in normal operation 1 receive buffer 2 is mask for buffer 3 global enable global mask 0 normal operation 1 highest defined mask is active for all following buffers 330 chapter 17 can controller user?s manual u15251ee4v0ud00 figure 17-47: mask control register (2/2) the following table shows which compare takes place for the different receive buffers. the id in this table always represents the id stored in the mentioned receive buffer. the table also shows which buffers are used to provide the mask information and therefore do not receive messages. a global mask can be used for standard and extended frames at the same time. the frame type is only controlled by the ide bit of the receiving buffer. ssht al function 0 x single shot mode disabled 10 single shot mode enabled; no re-transmission when an error occurs. transmit message will not be queued for a second transmit request when the arbitration was lost 11 single shot mode enabled; no re-transmission when an error occurs. transmit message will be queued for a second transmit request when the arbitration was lost. brprs7 brprs6 prescaler values 0 0 selects 0 - 64 dcan clocks per time quanta 0 1 selects 65 - 128 dcan clocks per time quanta 1 0 selects 129 - 192 dcan clocks per time quanta 1 1 selects 193 - 256 dcan clocks per time quanta table 17-26: mask operation buffers global msk1 msk0 receive buffer operation 01234-15 x00 compare id compare id compare id compare id compare id normal 0 0 1 mask0 compare id & mask0 compare id compare id compare id one mask 010 compare id compare id mask1 compare id & mask1 compare id one mask 0 1 1 mask0 compare id & mask0 mask1 compare id & mask1 compare id two masks 1 0 1 mask0 compare id & mask0 compare id & mask0 compare id & mask0 global mask 110 compare id compare id mask1 compare id & mask1 two normal, rest global mask 1 1 1 mask0 compare id & mask0 mask1 compare id & mask1 one mask, rest global mask 331 chapter 17 can controller user?s manual u15251ee4v0ud00 priority of receive buffers during compare it is possible that more than one receive buffer is configured to receive a particular message. for this case an arbitrary rule for the storage of the message into one of several matching receive buffers becomes effective. the priority of a receive buffers depends on its type defined by the setup of the mask register in first place and its number in second place. the rules for priority are: all non-masked receive buffers have a higher priority than the masked receive buffer. lower numbered receive buffers have higher priority. examples : 1. all rx buffers are enabled to receive the same standard identifier 0x7ffh. result: the message with identifier 0x7ffh is stored in rx0. 2. in difference to the previous set up, the mask option is set for rx2. again the message 0x7ffh is stored in buffer in rx0. 3. if additionally rx0 is configured as a mask, the message will be stored in rx4. 332 chapter 17 can controller user?s manual u15251ee4v0ud00 17.15.4 special functions (1) redefinition control register (redef) this register controls the redefinition of an identifier of a received buffer. redef can be written with an 1-bit or an 8-bit memory manipulation instruction. reset input sets redef to 00h. figure 17-48: redefinition control register (1/2) the redefinition register provides a way to change identifiers and other control information for one receive buffer, without disturbing the operation of the other buffers. this bit is cleared when init bit in canc is set. symbol<7>6543210addressafter reset redef def 0 0 0 sel3 sel2 sel1 sel0 ffb3h 00h r/w r r r r/w r/w r/w r/w def redefine permission bit 0 normal operation 1 receive operation for selected message is disabled. cpu can change definition data for this message. 333 chapter 17 can controller user?s manual u15251ee4v0ud00 figure 17-48: redefinition control register (2/2) cautions: 1. keep special programming sequence. failing to do so can cause inconsistent data or loss of receive data. 2. do not change def bit and sel bit at the same time. change sel bit only when def bit is cleared. 3. write first sel with def cleared. write than sel with def, or use bit manipulation instruction. only clear def bit by keep ing sel or use bit manipulation instruc- tion. setting the redefinition bit removes the selected receive buffer from the list of possible id hits during identifier comparisons. setting the def bit will not have immediate effect, if dcan is preparing to store or is already in progress of storing a received message into the particular buffer. in this case the redefinition request is ignored for the currently processed message. the application should monitor the dn flag before requesting the redefinition state for a particular buffer. a dn flag set indicates a new message that arrived or a new message that is in progress of being stored to that buffer. the application should be prepared to receive a message immediately after redefinition state was set. the user can identify this situation because the data new bit (dn) in the receive buffer will be set. this is of special importa nce if it is used toge ther with a ma sk function because in this case the dcan also writes the identifier part of the message to the receive buffer. then the application needs to re-write the configuration of the message buffer. sel3 sel2 sel1 sel0 buffer selection (n =0...15) 0000buffer 0 is selected for redefinition 0001buffer 1 is selected for redefinition 0010buffer 2 is selected for redefinition 0011buffer 3 is selected for redefinition 0100buffer 4 is selected for redefinition 0101buffer 5 is selected for redefinition 0110buffer 6 is selected for redefinition 0111buffer 7 is selected for redefinition 1000buffer 8 is selected for redefinition 1001buffer 9 is selected for redefinition 1010buffer 10 is selected for redefinition 1011buffer 11 is selected for redefinition 1100buffer 12 is selected for redefinition 1101buffer 13 is selected for redefinition 1110buffer 14 is selected for redefinition 1111buffer 15 is selected for redefinition other than above setting prohibited 334 chapter 17 can controller user?s manual u15251ee4v0ud00 17.16 interrupt information 17.16.1 interrupt vectors the dcan peripheral supports four interrupt sources as shown in the following table. 17.16.2 transmit interrupt the transmit interrupt is generated w hen all following cond itions are fulfilled: the transmit interrupt 0 is generated when txrq0 bit is cleared. the transmit interrupt 1 is generated when txrq1 bit is cleared. clearing of these bits releases the buffer for writing a new message into it. this event can occur due to a successful transmission or due to an abort of a transmission. only the dcan can clear this bit. the cpu can only request to clear the txrqn bit by setting the abortn bit (n = 0, 1). 17.16.3 receive interrupt the receive interrupt is generated when all of the following co nditions are fulfilled: can protocol part marks received frame valid. the received frame passes the acceptance filter. in other words, a message buffer with an identifier/mask combination fits to the received frame. the memory access engine successfully stored data in the message buffer. the message buffer is marked for interrupt generation with eni bit set. the memory access engine can delay the interrupt up to the 7th bit of the next frame because of its compare and store operations. table 17-27: interrupt sources function source interrupt flag error error counter overrun error wake up ceif receive received frame is valid crif transmit buffer 0 txrq0 is cleared ctif0 transmit buffer 1 txrq1 is cleared ctif1 335 chapter 17 can controller user?s manual u15251ee4v0ud00 17.16.4 error interrupt the error interrupt is generated when any of the following conditions are fulfilled: transmission error counter (boff) changes its state. transmission error counter status (tecs) changes its state. reception error counter status (recs) changes its state. overrun during ram access (over) becomes active. the wake-up condition (wake) becomes active. the wake-up condition activates an internal signal to the interrupt controller. in order to receive further error interrupts generated by other conditions, the cpu needs to cl ear the wake bit in canes register every time a wake-up condition was recognized. no further interrupt can be detected by the cpu as long as the wake bit is set. 336 chapter 17 can controller user?s manual u15251ee4v0ud00 17.17 influence of the standby function of the can controller 17.17.1 cpu halt mode the cpu halt mode is possible in conjunction with dcan sleep mode. 17.17.2 cpu stop mode the dcan stops any activity when its clock supply stops due to a cpu stop mode issued. this may cause an erroneous behaviour on the can bus. entering the cpu stop mode is not allowed when the dcan is in normal mode, i.e. online to the can bus. the dcan will reach an overrun condition, when it receives clock supply again. cpu stop mode is possible when the dcan was set to initialization state, sleep mode or stop mode beforehand. note that the cpu will not be start ed again if the dcan stop m ode was entered previously. 17.17.3 dcan sleep mode the dcan sleep mode is intended to lower the power consumption during phases where no communi- cation is required. the cpu requests the dcan sleep mode. the dcan will signal with the wake bit, if the request was granted or if it is not possible to enter the sleep mode due to ongoing bus activities. after a successful switch to the dcan sleep mode, the cpu can safely go into halt, watch or stop mode. however, the application needs to be prepared that the dcan cancels the sleep mode any time due to bus activities. if the wake-up interrupt is serviced, the cpu stop mode has not to be issued. otherwise the cpu will not be releas ed from cpu stop mode even when there is ongoing bus activity. the wake-up is independent from the clock. the release time for the cpu stop mode of the device is of no concern because the dcan synchronizes agai n to the can bus after clock supply has started. 337 chapter 17 can controller user?s manual u15251ee4v0ud00 the following example sketches the general approach on how to enter the dcan sleep mode. note that the function may not return for infinite time when the can bus is busy. the user may apply time out controls to avoid excessive run-times. code example: dcan_sleep_mode(void){ canes = 0x02; // clear wake bit canc = 0x04 // request dcan sleep mode while (canes & 0x02) // check if dcan sleep mode was accepted { canes = 0x02; // try again to get dcan asleep canc = 0x04; } } the following code example assures a safe transition into cpu stop mode for all timing scenarios of a suddenly occurring bus activity. t he code prevents that the cpu get s stuck with its oscillator stopped despite can bus activity. code example: ........ //any application code dcan_sleep_mode; //request and enter dcan sleep mode ........ //any application code di(); //disable interrupts nop; note nop; if (wakeup_interrupt_occurred == false) // the variable wakeup_interrupt occurred // needs to be initialized at system reset // and it needs to be set true when servicing // the wake-up interrupt. { cpu_stop; //enter cpu stop mode } nop: note nop: nop; ei(); // enable interrupts ......... // resume with application code note: the interrupt acknowledge needs some clock cycles (depends on host core). in order to prevent that the variable wakeup_interrupt_occurred is already read before di(); becomes effective some nop-instruction have to be inserted. as well the number of nop-instructions after the cpu stop instruction is dependent on the host core. the given example is tailored for 78k0. 338 chapter 17 can controller user?s manual u15251ee4v0ud00 17.17.4 dcan stop mode the cpu requests this mode from dcan. the procedure equals the request for dcan sleep mode. the dcan will signal with the wake bit, if the request was granted or if it is not possible to enter the dcan stop mode due to ongoing bus activities. after a successful switch to the dcan stop mode, the cpu can safely go into halt, watch or stop mode without any precautions. the dcan can only be woken up by the cpu. therefore the cpu needs to clear the sleep bit in the canc register. this mode reduces the power consumption of the dcan to a minimum. code example: dcan_stop_mode(void){ canes = 0x02; // clear wake bit canc = 0x06 // request dcan stop mode while (canes & 0x02) // check if dcan stop mode was accepted { canes = 0x02; // try again to get dcan into stop mode canc = 0x06; } } 339 chapter 17 can controller user?s manual u15251ee4v0ud00 17.18 functional description by flowcharts 17.18.1 initialization figure 17-49: initialization flow chart software init end initialization reset set init=1 in canc set brprs sync0/1 initilialize message and mask data set mcnt maskc clear init=0 in canc write for brprs sync0/1 mcnt maskc is now disabled 340 chapter 17 can controller user?s manual u15251ee4v0ud00 17.18.2 transmit preparation figure 17-50: transmit preparation transmit txrqn write data select priority txp set txrqn = 1 end transmit = 0 wait or abort or try other buffer = 1 341 chapter 17 can controller user?s manual u15251ee4v0ud00 17.18.3 abort transmit figure 17-51: transmit abort transmission abort set txan txrqn = 1 txcn = 0 transmit was successful before abort transmit was aborted = 0 end transmission abort = 1 342 chapter 17 can controller user?s manual u15251ee4v0ud00 17.18.4 handling by the dcan figure 17-52: handling of semaphore bits by dcan-module data storage write dn = 1 muc = 1 write dn = 1 muc = 0 dlc end data storage warns that data will be changed data is changed. muc = 0 signals stable data write identifier bytes only for buffers that are declared for mask operation write data bytes 343 chapter 17 can controller user?s manual u15251ee4v0ud00 17.18.5 receive event oriented figure 17-53: receive with interrupt, software flow receive interrupt scans rmes or dn bits to find message clear dn bit read or process data dn = 0 and muc = 0 end receive interrupt yes uses clr1 command data was changed by can during the processing clear interrupt no 344 chapter 17 can controller user?s manual u15251ee4v0ud00 17.18.6 receive task oriented figure 17-54: receive, software polling receive polled clear dn bit read or process data dn = 0 and muc = 0 end receive polled yes uses clr1 command data was changed by can during the processing no 345 chapter 17 can controller user?s manual u15251ee4v0ud00 17.19 can controller precautions (1) resynchronization according to the can protocol specification (bos ch can specification, version 2.0, sept. 1991, part a, chapter 8) a can node has to perform a soft-synchronization, when acting as a transmitter sending a dominant bit, if a recessive to dominant edge occurs after the sample point within phase segment 2. this scenario is only encountered in case of a disturbance. for this case the soft-syn- chronization is not performed by the implementations listed below. due to this, the nominal length of an error frame, that follows this disturbance, can be extended by the amount of time quanta, allocated for the synchronization jump width. 346 user?s manual u15251ee4v0ud00 [memo] 347 user?s manual u15251ee4v0ud00 chapter 18 interrupt functions 18.1 interrupt function types the following three types of interrupt functions are used. (1) non-maskable interrupt this interrupt is acknowledged unconditionally even in a disabled state. it does not undergo inter- rupt priority control and is given top priority over all other interrupt requests. it generates a standby release signal. the non-maskable interrupt has one source of interrupt request from the watchdog timer. (2) maskable interrupts these interrupts undergo mask control. maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specify flag register. multiple high priority interrupts can be applied to low priority interrupts. if two or more interrupts with the same priority are simultaneously generated, each interrupts has a predetermined priority (see table 18-1, ?interrupt source list,? on page 348). a standby release signal is generated. the maskable interrupt has seven sources of external interrupt requests and fifteen sources of internal interrupt requests. (3) software interrupt this is a vectored interrupt to be generated by executing the brk instruction. it is acknowledged even in a disabled state. the software interrupt does not undergo interrupt priority control. 348 chapter 18 interrupt functions user?s manual u15251ee4v0ud00 18.2 interrupt sources and configuration there are total of 26 interrupt sources: non-maskable, maskable, and software interrupts. notes: 1. default priorities are intended for two or more simultaneously generated maskable interrupt requests. 0 is the highest priority and 25 is the lowest priority. 2. basic configuration types (a) to (e) correspond to (a) to (e) of figure 18-1on page 349. table 18-1: interrupt source list mask- ability interrupt priority note 1 interrupt source internal/ external vector address basic structure ty p e note 2 name trigger non- maskable _intwdt overflow of watchdog timer (when the watchdog timer nmi is selected) internal 0004h (a) maskable 0intwdt overflow of watchdog timer (when the interval timer mode is selected) (b) 1 intad end of a/d converter conversion 0006h 2 intovf overflow of 16-bit timer 2 0008h 3inttm20 generation of 16-bit timer capture register (cr20) match signal 000ah 4inttm21 generation of 16-bit timer capture register (cr21) match signal 000ch 5inttm22 generation of 16-bit timer capture register (cr22) match signal 000eh 6intp0 pin input edge detection external 0010h (c) 7 intp1 0012h 8 intp2 0014h 9 intp3 0016h 10 intce can error internal 0018h (d) 11 intcr can receive 001ah 12 intct0 can transmit buffer 0 001ch 13 intct1 can transmit buffer 1 001eh 14 intcsi20 end of serial interface sio20 transfer 0020h 15 intser serial interface uart reception error generation 0022h 16 intsr end of serial interface uart reception 0024h 17 intst end of serial interface uart transfer 0026h 18 inttm00 generation of 16-bit timer 0 capture/compare register (cr00) match signal 0028h 19 inttm01 generation of 16-bit timer 0 capture/compare register (cr01) match signal 002ah 20 inttm50 generation of 8-bit timer/event counter 50 match signal 002ch 21 inttm51 generation of 8-bit timer/event counter 51 match signal 002eh 22 intwti reference time interval signal from watch timer 0032h 23 intwt reference time interval signal from watch timer 0034h 24 intkr key return interrupt signal 0036h (e) 25 intcsi30 end of serial interface sio30 transfer 0038h (d) software _ brk brk instructio n execution internal 003eh (d) 349 chapter 18 interrupt functions user?s manual u15251ee4v0ud00 figure 18-1: basic configuration of interrupt function (1/2) (a) internal non-maskable interrupt (b) internal maskable interrupt remark: if : interrupt request flag ie : interrupt enable flag isp : in-service priority flag mk : interrupt mask flag pr : priority specify flag internal bus priority control circuit vector table address generator standby release signal interrupt request internal bus ie pr isp mk if interrupt request priority control circuit vector table address generator standby release signal 350 chapter 18 interrupt functions user?s manual u15251ee4v0ud00 figure 18-1: basic configuration of interrupt function (2/2) (c) external maskable interrupt (d) external maskable interrupt (intkr) (e) software interrupt remark: if : interrupt request flag ie : interrupt enable flag isp : in-service priority flag mk : interrupt mask flag pr : priority specify flag external interrupt mode register (egn, egp) edge detector interrupt request ie pr isp mk if priority control circuit vector table address generator standby release signal internal bus falling edge detector interrupt request ie pr isp mk if priority control circuit vector table address generator standby release signal internal bus internal bus priority control circuit vector table address generator interrupt request 351 chapter 18 interrupt functions user?s manual u15251ee4v0ud00 18.3 interrupt function control registers the following six types of registers are used to control the interrupt functions. interrupt request flag register (if0l, if0h, if1l, if1h) interrupt mask flag register (mk0l, mk0h, mk1l, mk1h) priority specify flag register (pr0l, pr0h, pr1l, pr1h) external interrupt mode register (egp, egn) program status word (psw) table 18-2 gives a listing of interrupt request flags, interrupt mask flags, and priority specify flags corre- sponding to interrupt request sources. table 18-2: various flags corresponding to interrupt request sources interrupt request signal name interrupt request flag interrupt mask flag priority specify flag intp0 pif0 pmk0 ppr0 intp1 pif1 pmk1 ppr1 intp2 pif2 pmk2 ppr2 intp3 pif3 pmk3 ppr3 inttm00 tmif00 tmmk00 tmpr00 inttm01 tmif01 tmmk01 tmpr01 intovf ovfif ovfmk ovfpr inttm20 tmif20 tmmk20 tmpr20 inttm21 tmif21 tmmk21 tmpr21 inttm22 tmif22 tmmk22 tmpr22 intm50 tmif50 tmmk50 tmpr50 intm51 tmif51 tmmk51 tmpr51 intm52 tmif52 tmmk52 tmpr52 intwti wtiif wtimk wtipr intwt wtif wtmk wtpr intwdt wdtif wdtmk wdtpr intad adif admk adpr intcsi20 csiif20 csimk20 csipr20 intser serif sermk serpr intsr srif srmk srpr intst stif stmk stpr intce ceif cemk cepr intcr rrf crmk crpr intct0 ctif0 ctmk0 ctpr0 intct1 ctif1 ctmk1 ctpr1 intkr krif krmk krpr intcsi30 csiif30 csimk30 csipr30 352 chapter 18 interrupt functions user?s manual u15251ee4v0ud00 (1) interrupt request flag registers (if0l, if0h, if1l, if1h) the interrupt request flag is set to 1 when the corresponding interrupt request is generated. it is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of reset input. if0l, if0h, if1l and if1h are set with an 1-bit or an 8-bit memory manipulation instruction. if if0l and if0h are used as a 16-bit register if0, use a 16-bit memory manipulation instruction for the setting. reset input sets these registers to 00h. figure 18-2: interrupt request flag register format cautions: 1. tmif4 flag is r/w enabled only when the watchdog timer is used as an interval timer. if used in the watchdog timer mode 1, set tmif4 flag to 0. 2. set always 0 in if1h bit 3 to bit 7. symbol <7> <6> <5> <4> <3> <2> <1> <0> address after reset r/w if0l pif1 pif0 tmif22 tmif21 tmif20 ovfif adif tmif4 ffe0h 00h r/w if0h serif csiif30 ctif1 ctif0 crif ceif pif3 pif2 ffe1h 00h r/w if1l wtif 0 tmif51 tmif50 tmif0 1 tmif00 stif srif ffe2h 00h r/w if1h00000csiif30krifwtifffe3h00hr/w xxifx interrupt request flag 0 no interrupt request signal 1 interrupt request signal is generated; interrupt request state 353 chapter 18 interrupt functions user?s manual u15251ee4v0ud00 (2) interrupt mask flag registers (mk0l, mk0h, mk1l, mk1h) the interrupt mask flag is used to enable/disable the corresponding maskable interrupt service. mk0l, mk0h, mk1l and mk1h are set with an 1-bit or an 8-bit memory manipulation instruction. if mk0l and mk0h are used as a 16-bit register mk0, use a 16-bit memory manipulation instruc- tion for the setting. reset input sets these registers to ffh. figure 18-3: interrupt mask flag register format cautions: 1. if tmmk4 flag is read when the watchdog timer is used as a non-maskable interrupt, mk0 value becomes undefined. 2. set always 1 in mk1h bit 3 to bit 7. symbol <7> <6> <5> <4> <3> <2> <1> <0> address after reset r/w mk0l pmk1 pmk0 tmmk22 tmmk21 tmmk20 ovfmk admk tmmk4 ffe4h ffh r/w mk0h sermk csimk20 ctmk1 ctmk0 crmk cemk pmk3 pmk2 ffe5h ffh r/w mk1l wtmk 1 tmmk51 tmmk50 tmmk01 tmmk00 stmk srmk ffe6h ffh r/w mk1h 1 1 1 1 1 csimk30 krmk wtmk ffe7h ffh r/w xxmkx interrupt servicing control 0 interrupt servicing enabled 1 interrupt servicing disabled 354 chapter 18 interrupt functions user?s manual u15251ee4v0ud00 (3) priority specify flag registers (pr0l, pr0h, pr1l, pr1h) the priority specify flag is used to set the co rresponding maskable interrupt priority orders. pr0l, pr0h, pr1l and pr1h are set with an 1-bit or an 8-bit memory manipulation instruction. if pr0l and pr0h are used as a 16-bit register pr0, use a 16-bit memory manipulation instruction for the setting. reset input sets these registers to ffh. figure 18-4: priority specify flag register format cautions: 1. when a watchdog timer is used as a non-maskable interrupt, set 1 to tmpr4 flag. 2. set always 1 in pr1h bit 3 to bit 7. symbol <7> <6> <5> <4> <3> <2> <1> <0> address after reset r/w pr0l ppr1 ppr0 tmpr22 tmpr21 tmpr20 ovfpr adpr tmpr4 ffe8h ffh r/w pr0h serpr csipr20 ctpr1 ctpr0 crpr cepr ppr3 ppr2 ffe9h ffh r/w pr1l wtpr 1 tmpr51 tmpr50 tmpr01 tmpr00 stpr srpr ffeah ffh r/w pr1h 1 1 1 1 1 csipr30 krpr wtpr ffebh ffh r/w xxprx priority level selection 0 high priority level 1 low priority level 355 chapter 18 interrupt functions user?s manual u15251ee4v0ud00 (4) external interrupt rising edge enable register (egp), external interrupt falling edge enable register (egn) egp and egn specify the valid edge to be detected on pins p00 to p03. egp and egn can be read or written to with an 1-bit or an 8-bit memory manipulation instruction. these registers are set to 00h when the reset signal is output. figure 18-5: formats of external interrupt rising edge enable register and external interrupt falling edge enable register symbol76543210addressafter resetr/w egp 0 0 0 0 egp3 egp2 egp1 egp0 ff48h 00h r/w symbol76543210addressafter resetr/w egn 0 0 0 0 egn3 egn2 egn1 egn0 ff49h 00h r/w egpn egnn valid edge of intpn pin (n = 0 - 3) 0 0 interrupt disable 0 1 falling edge 1 0 rising edge 1 1 both rising and falling edges 356 chapter 18 interrupt functions user?s manual u15251ee4v0ud00 (5) program status word (psw) the program status word is a register to hold the instruction execution result and the current status for interrupt request. the ie flag to set maskable interrupts (enable/disable) and the isp flag to control multiple interr upt servicing are mapped. besides 8-bit unit read/write, this register can carry out operations with a bit manipulation instruc- tion and dedicated instructions (ei and di). when a vectored interrupt request is acknowledged, and when the brk instruction is executed, the contents of psw automatically is saved onto the stack and the ie flag is reset to 0. if a maskable interrupt request is acknowledged contents of the priority specify flag of the acknowledged interrupt are transferred to the isp flag. the acknowl- edged contents of psw is also saved onto the stack with the push psw instruction. it is retrieved from the stack with the reti, retb, and pop psw instructions. reset input sets psw to 02h. figure 18-6: program status word format symbol76543210after resetr/w psw ie z rbs1 ac rbs0 0 isp cy 02h r/w isp priority of interrupt currently being received 0 high-priority interrupt servicing (low-priority interrupt disable) 1 interrupt request not acknowledged or low-priority interrupt servicing (all-maskable interrupts enable) ie interrupt request acknowledge enable/disable 0disable 1enable 357 chapter 18 interrupt functions user?s manual u15251ee4v0ud00 18.4 interrupt servicing operations 18.4.1 non-maskable interrupt request acknowledge operation a non-maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledge disable state. it does not undergo interrupt priority control and has highest priority over all other interrupts. if a non-maskable interrupt request is acknowledged, psw and pc are pushed on the stack. the ie and isp flags are reset to 0, and the vector table contents are loaded into pc. a new non-maskable interrupt request generated during execution of a non-maskable interrupt servic- ing program is acknowledged after the current execution of the non-maskable interrupt servicing pro- gram is terminated (following reti instruction execution) and one main routine instruction is executed. if a new non-maskable interrupt request is generated twice or more during a non-maskable interrupt service program execution, only one non-maskable interrupt request is acknowledged after termination of the non-maskable interrupt service program execution. figure 18-7: flowchart from non-maskable interrupt generation to acknowledge remark: wdtm : watchdog timer mode register wdt : watchdog timer wdtm4 = 1 (with watchdog timer mode selected)? overflow in wdt? wdtm3 = 0 (with non-maskable interrupt selected)? interrupt request generation wdt interrupt servicing? interrupt control register unaccessed? interrupt service start interrupt request held pending reset processing interval timer start no ye s ye s no ye s no ye s no ye s no 358 chapter 18 interrupt functions user?s manual u15251ee4v0ud00 figure 18-8: non-maskable interrupt request acknowledge timing remark: wdtif : watchdog timer interrupt request flag figure 18-9: non-maskable interrupt request acknowledge operation (a) if a new non-maskable interrupt request is generated during non-maskable interrupt servicing program execution (b) if two non-maskable interrupt requests are generated during non-maskable interrupt servicing program execution instruction instruction cpu instruction tmif4 psw and pc save, jump to interrupt servicing interrupt sevicing program nmi request nmi request 1 instruction execution main routine nmi request reserve reserved nmi request processing nmi request nmi request 1 instruction execution main routine reserved although two or more nmi requests have been generated, only one request has been acknowledged. nmi request reserved 359 chapter 18 interrupt functions user?s manual u15251ee4v0ud00 18.4.2 maskable interrupt request acknowledge operation a maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the interrupt mask (mk) flag is cleared to 0. a vectored interrupt request is acknowledged in an interrupt enable state (with ie flag set to 1). however, a low-priority interrupt request is not acknowledged during high-priority interrupt service (with isp flag reset to 0). wait times from maskable interrupt request generation to interrupt servicing are as follows. note: if an interrupt request is generated just before a divide instruction, the wait time is maximized. remark: 1 clock: 1/ f cpu (f cpu : cpu clock) if two or more maskable interrupt requests are generated simultaneously, the request specified for higher priority with the priority specify flag is ackno wledged first. if two or more requests are specified for the same priority with the priority specify flag, the interrupt request with the higher default priority is acknowledged first. any reserved interrupt requests are acknowledged when they become acknowledgeable. figure 18-10 on page 360 shows interrupt request acknowledge algorithms. when a maskable interrupt request is acknowledged, the contents of program status word (psw) and program counter (pc) are saved in this order onto the stack. then, the ie flag is reset (to 0), and the value of the acknowledged interrupt priority specify flag is transferred to the isp flag. further, the vector table data determined for each interrupt request is loaded into pc and the program will branch accordingly. return from the interrupt is possible with the reti instruction. table 18-3: times from maskable interrupt request generation to interrupt service minimum time maximum time note when xxprx = 0 7 clocks 32 clocks when xxprx = 1 8 clocks 33 clocks 360 chapter 18 interrupt functions user?s manual u15251ee4v0ud00 figure 18-10: interrupt request acknowledge processing algorithm remark: xxif : interrupt request flag xxmk : interrupt mask flag xxpr : priority specify flag ie : flag to control maskable interrupt request acknowledge isp : flag to indicate the priority of interrupt being serviced (0 = an interrupt with higher priority is being serviced, 1 = interrupt request is not acknowledged or an interrupt with lower priority is being serviced). star t xxif = 1? xxmk = 0? xxpr = 0? any simultaneously generated xxpr = 0 interrupts? ie = 1? isp = 1? vectored interrupt servicing interrupt request reserve interrupt request reserve interrupt request reserve interrupt request reserve interrupt request reserve interrupt request reserve interrupt request reserve vectored interrupt servicing any high- prior ity interrupt among simultaneously generated xxpr = 0 interrupts? ie = 1? yes (high priority) ye s no ye s no no no yes (interrupt request generation) no ye s no (low priority) ye s ye s no ye s ye s no no any simultaneously generated high-priority interrupts? 361 chapter 18 interrupt functions user?s manual u15251ee4v0ud00 figure 18-11: interrupt request acknowledge timing (minimum time) remark: 1 clock: 1/ f cpu (f cpu : cpu clock) figure 18-12: interrupt request acknowledge timing (maximum time) remark: 1 clock: 1/ f cpu (f cpu : cpu clock) instruction instruction psw and pc save, jump to interrupt servicing 6 clocks interrupt servicing program 8 clocks 7 clocks cpu processing xxif (xxpr = 1) xxif (xxpr = 0) instruction divide instruction psw and pc save, jump to interrupt servicing 6 clocks interrupt servicing program 33 clocks 32 clocks cpu processing xxif (xxpr = 1) xxif (xxpr = 0) 25 clocks 362 chapter 18 interrupt functions user?s manual u15251ee4v0ud00 18.4.3 software interrupt request acknowledge operation a software interrupt request is acknowledged by brk instruction execution. software interrupt cannot be disabled. if a software interrupt is acknowledged, the contents of program status word (psw) and program coun- ter (pc) are saved to stacks, in this order. then the ie flag is reset (to 0), and the contents of the vector tables (003eh and 003fh) are loaded into pc and the program branches accordingly. return from the software interrupt is possible with the retb instruction. caution: do not use the reti instruction for returning from the software interrupt. 18.4.4 multiple interrupt servicing a multiple interrupt service consists in acknowledging another interrupt during the execution of another interrupt routine. a multiple interrupt service is generated only in the interrupt request acknowledge enable state (ie = 1) (except non-maskable interrupt). as soon as an interrupt request is acknowledged, it enters the acknowledge disable state (ie = 0). therefore, in order to enable multiple interrupts, it is necessary to set the interrupt enable state by setting the ie flag (1) with the ei instruction during interrupt servicing. even in an interrupt enabled state, a multiple interrupt may not be en abled. however, it is controlled according to the interrupt priority. there are two priorities, the default priority and the programmable pri- ority. the multiple interrupt is controlle d by the programmable priority control. if an interrupt request with the same or higher priority than that of the interrupt being serviced is gener- ated, it is acknowledged as a multiple interrupt. in the case of an interrupt with a priority lower than that of the interrupt being processed, it is not acknowledged as a multiple interrupt. an interrupt request not acknowledged as a multiple interrupt due to interrupt disable or a low priority is reserved and acknowledged following one instruction execution of the main processing after the com- pletion of the interrupt being serviced. during non-maskable interrupt servicing, multiple interrupts are not enabled. table 18-4 on page 363 shows an interrupt request enabled for multiple interrupt during interrupt servic- ing, and figure 18-13 on page 364 shows multiple interrupt examples. 363 chapter 18 interrupt functions user?s manual u15251ee4v0ud00 remarks: 1. e : multiple interrupt enable 2. d : multiple interrupt disable 3. isp and ie are the flags contained in psw isp = 0 : an interrupt with higher priority is being serviced isp = 1 : an interrupt request is not accepted or an interrupt with lower priority is being serviced ie = 0 : interrupt request acknowledge is disabled ie = 1 : interrupt request acknowledge is enabled 4. xxpr is a flag contained in pr0l, pr0h, and pril xxpr = 0 : higher priority level xxpr = 1 : lower priority level table 18-4: interrupt request enabled for mu ltiple interrupt during interrupt servicing maskable interrupt request non-maskable interrupt request maskable interrupt request xxpr = 0 xxpr = 1 interrupt being serviced ie = 1 ie = 0 ie = 1 ie = 0 non-maskable interrupt d d d d d maskable interrupt isp = 0 e e d d d isp = 1e eded software interrupt e e d e d 364 chapter 18 interrupt functions user?s manual u15251ee4v0ud00 figure 18-13: multiple interrupt example (1/2) (a) example 1. two multiple interrupts generated during interrupt intxx servicing, two interrupt requests, intyy and intzz are acknowledged, and a mul- tiple interrupt is generated. an ei instruction is issued before each interrupt request acknowledge, and the interrupt request acknowledge enable state is set. (b) example 2. multiple interrupt is not generated by priority control the interrupt request intyy generated during interrupt intxx servicing is not acknowledged because the interrupt priority is lower than that of intxx, and a multiple interrupt is not generated. intyy request is retained and acknowledged after execution of 1 instruction execution of the main processing. remark: pr = 0 : higher priority level pr = 1 : lower priority level ie = 0 : interrupt request acknowledge disable main processing ei intxx (pr = 1) intyy (pr = 0) ie = 0 ei reti intxx servicing intzz (pr = 0) ie = 0 ei reti intyy servicing ie = 0 reti intzz servicing main processing intxx servicing intyy servicing intxx (pr = 0) 1 instruction execution ie = 0 intyy (pr = 1) ei ie = 0 ei reti reti 365 chapter 18 interrupt functions user?s manual u15251ee4v0ud00 figure 18-13: multiple interrupt example (2/2) (c) example 3. a multiple interrupt is not generated because interrupts are not enabled because interrupts are not enabled in interrupt intxx servicing (an ei instruction is not issued), inter- rupt request intyy is not acknowledged, and a multiple interrupt is not generated. the intyy request is reserved and acknowledged after 1 instruction execution of the main processing. remark: pr = 0 : higher priority level ie = 0 : interrupt request acknowledge disable main processing intxx servicing intyy servicing intxx (pr = 0) 1 instruction execution ie = 0 intyy (pr = 0) ie = 0 reti reti ei 366 chapter 18 interrupt functions user?s manual u15251ee4v0ud00 18.4.5 interrupt request reserve some instructions may reserve the acknowledge of an instruction request until the completion of the execution of the next instruction even if the interrupt request is generated during the execution. the following list shows such instructions (interrupt request reserve instruction). mov psw, #byte mov a, psw mov psw, a mov1 psw.bit, cy mov1 cy, psw.bit and1 cy, psw.bit or1 cy, psw.bit xor cy, psw.bit set1/clr1 psw.bit retb reti push psw pop psw bt psw.bit, $addr16 bf psw.bit, $addr16 btclr psw.bit, $addr16 ei di manipulate instructions: for if0l, if0h, if1l, mk0l, mk0h, mk1l, pr0l, pr0h, pr1l, egp, egn caution: brk instruction is not an interrupt request reserve instruction described above. however, in a software interrupt started by the execution of brk instruction, the ie flag is cleared to 0. therefore, interrupt requests are not acknowledged even when a maskable interrupt request is issued during the execution of the brk instruction. however, non-maskable interrupt requests are acknowledged. 367 chapter 18 interrupt functions user?s manual u15251ee4v0ud00 figure 18-14 shows the interrupt request hold timing. figure 18-14: interrupt request hold remarks: 1. instruction n: instruction that holds interrupts requests 2. instruction m: instructions other than interrupt request pending instruction 3. the xxpr (priority level) values do not affect the operation of xxif (interrupt request). cpu processing xxif instruction n instruction m save psw and pc, jump to interrupt service interrupt service program 368 user?s manual u15251ee4v0ud00 [memo] 369 user?s manual u15251ee4v0ud00 chapter 19 key return mode 19.1 key return mode functions the key return mode allows it to bu ild up a keyboard by using a detection of a low level at any bit of port 4. caution: when the key return mode is enabled, a low level at any bit of port 4 generates a key return interrupt. port pins that should not generate a key return interrupt can be disabled by switching the respective port pin to output mode. 19.2 key return mode circuit configuration the key return mode consists of the following hardware. figure 19-1: key return mode circuit block diagram table 19-1: key return mode configuration item configuration control register key return mode register (krm) port mode register 4 (pm4) intkr falling edge detection circuit kr0/p40 i/o logic kr1/p41 i/o logic kr6/p46 i/o logic kr7/p47 i/o logic kr 370 chapter 19 key return mode user?s manual u15251ee4v0ud00 19.3 key return mode control registers the following two types of registers are used to control the key return mode: key return mode register (krm) port mode register (pm4) (1) key return mode register (krm) the register enables the key return mode. krm is set with an 1-bit or an 8-bit memory manipula- tion instruction. reset input sets krm to 00h. figure 19-2: key return mo de register (krm) format caution: when the key return mode is enabled, a low level at any bit of port 4 generates a key return interrupt. port pins that should not generate a key return interrupt can be disabled by switching the respective port pin to output mode. symbol7 6 54321<0>addressafter resetr/w krm 0 0 0 0 0 0 0 kr ff47h 00h r/w kr key return mode selection 0 key return mode disabled 1 key return mode enabled 371 chapter 19 key return mode user?s manual u15251ee4v0ud00 (2) port mode register 4 (pm4) this register sets port 4 in input/output mode in 1-bit units. when using port 4 in key return mode, set pm4 to input. pm4 is set with an 1-bit or an 8-bit memory manipulation instruction. reset input sets pm4 to ffh. figure 19-3: port mode register 4 (pm4) format symbol 7 6 5 4 3 2 1 0 address after reset r/w pm4 pm47 pm46 pm45 pm44 pm43 pm42 pm41 pm40 ff24h ffh r/w pm4n p4n pin input/output mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) 372 user?s manual u15251ee4v0ud00 [memo] 373 user?s manual u15251ee4v0ud00 chapter 20 standby function 20.1 standby function and configuration 20.1.1 standby function the standby function is designed to decrease the power consumption of the system. the following two modes are available. (1) halt mode halt instruction execution sets the halt mode. the halt mode is intended to stop the cpu operation clock. system clock oscillator continue s oscillation. in this mo de, current consumption cannot be decreased as much as in the stop mode. the halt mode is capable of restart imme- diately upon interrupt request and to carry out intermittent operations such as watch applications. (2) stop mode stop instruction execution sets the stop mode. in the stop mode, the main system clock oscil- lator stops and the whole system stops. cpu current consumption can be considerably decreased. data memory low-voltage hold is possible. thus, the stop mode is effective to hold data memory contents with ultra-low current consumption. because this mode can be cleared upon interrupt request, it enables intermittent operations to be carried out. however, because a wait time is necessary to secure an oscillation stab ilization time after the stop mode is cleared, select the halt mode if it is necessary to start processing immediately upon interrupt request. in any mode, all the contents of the register, flag, and data memory just before entering the standby mode are held. the input/output port output latch and output buffer status are also held. cautions: 1. the stop mode can be used only when the system operates with the main sys- tem clock (subsystem clock oscillation cannot be stopped). the halt mode can be used with either the main system clock or the subsystem clock. 2. when proceeding to the stop mode, be sure to stop the peripheral hardware operation and execute the stop instruction afterwards. 3. the following sequence is recommended for power consumption reduction of the a/d converter when the standby function is used: first clear bit 7 (cs) to 0 to stop the a/d conversion operation, and then execute the halt or stop instruction. 374 chapter 20 standby function user?s manual u15251ee4v0ud00 20.1.2 standby function control register a wait time after the stop mode is cleared upon inte rrupt request till the oscillation stabilizes is control- led with the oscillation stabilizatio n time select register (osts). osts is set with an 8-bit memo ry manipulation instruction. reset input sets osts to 04h. however, it takes 2 17 /f x until the stop mode is cleared by reset input. figure 20-1: oscillation stabilization ti me select register (osts) format caution: the wait time after stop mode clear does not include the time (see ?a? in the figure 20-2 below) from stop mode clear to clock oscillation start, regardless of clearance by reset input or by interrupt generation. figure 20-2: standby timing remarks: 1. f x : main system clock oscillation frequency 2. values in parentheses apply to operating at f x = 8.00 mhz symbol76543210addressafter resetr/w osts00000osts2osts1osts0fffah04hr/w osts2 osts1 osts0 selection of oscillation stabilization time when stop mode is released 000 2 12 /f x (512 s) 001 2 14 /f x (2 ms) 010 2 15 /f x (4.1 ms) 111 2 16 /f x (8.9 ms) 100 2 17 /f x (16.38 ms) other than above setting prohibited stop mode clear x1 pin voltage waveform v ss a 375 chapter 20 standby function user?s manual u15251ee4v0ud00 20.2 standby function operations 20.2.1 halt mode (1) halt mode set and operating status the halt mode is set by executing the halt instruction. it can be set with the main system clock or the subsystem clock. the operating status in the halt mode is described below. table 20-1: halt mode operation status halt mode setting halt execution during main halt execution during system clock operation sub system clock operation item (main system clock stops) clock generator both main and subsystem clocks can be oscillated / clock supply to the cpu stops cpu operation stops port (output latch) status befo re halt mode setting is held 16-bit timer /event counte r (tm0) operable operation stops 16-bit timer (tm2) operable operation stops 8-bit timer event counter (tm50/ tm51) operable operable when ti is selected as count clock watch timer operable operable when f xt is selected as count clock watchdog timer operable operation stops a/d converter operation stops serial i/f operable operable at external sck can operation stops external interrupt (intp0 to intp3 and intkr) operable 376 chapter 20 standby function user?s manual u15251ee4v0ud00 (2) halt mode clear the halt mode can be cleared with the following four types of sources. (a) clear upon unmasked interrupt request an unmasked interrupt request is used to clear the halt mode. if interrupt acknowledge is ena- bled, vectored interrupt service is carried out. if disabled, the next address instruction is executed. figure 20-3: halt mode clear upon interrupt generation remarks: 1. the broken line indicates the case when the interrupt request which has cleared the standby status is acknowledged. 2. wait time will be as follows: when vectored interrupt service is carried out : 8 to 9 clocks when vectored interrupt service is not carried out : 2 to 3 clocks (b) clear upon non-maskable interrupt request the halt mode is cleared and vectored interrupt service is carried out whether interrupt acknowl- edge is enabled or disabled. halt instruction wait standby release signal operating mode clock halt mode wait oscillation operating mode 377 chapter 20 standby function user?s manual u15251ee4v0ud00 (c) clear upon reset input as is the case with normal reset operation, a program is executed after branch to the reset vector address. figure 20-4: halt mode release by reset input remarks: 1. f x : main system clock oscillation frequency 2. values in parentheses apply to operation at f x = 8.0 mhz remark: x: don?t care table 20-2: operation after halt mode release release source mkxx prxx ie isp operation maskable interrupt request 0 0 0 x next address instruction execution 0 0 1 x interrupt service execution 0101 next address instruction execution 01x0 0 1 1 1 interrupt service execution 1xxxhalt mode hold non-maskable interrupt request - - x x interrupt service execution reset input - - x x reset processing halt instruction reset signal operating mode clock reset period halt mode oscillation oscillation stop oscillation stabilization wait status operating mode oscillation wait (2 17 /f x : 16.3 ms) 378 chapter 20 standby function user?s manual u15251ee4v0ud00 20.2.2 stop mode (1) stop mode set and operating status the stop mode is set by executing the stop instruction. it can be set only with the main system clock. cautions: 1. when the stop mode is set, the x2 pin is internally connected to v dd via a pull- up resistor to minimize leakage current at the crystal oscillator. thus, do not use the stop mode in a system where an external clock is used for the main system clock. 2. because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt re quest flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. thus, the stop mode is reset to the halt mode immediately after execution of the stop instruction. after the wait time set using the oscillation stabilization time select register (osts), the operating mode is set. the operating status in the stop mode is described below. table 20-3: stop mode operating status smos mode setting with subsystem clock wit hout subsystem clock item clock generator only main system clock stops oscillation cpu operation stops port (output latch) status before stop mode setting is held 16-bit timer/event counter (tm00) operation stops 16-bit timer (tm2) operation stops 8-bit timer event counter 5 and 6 operable when ti is selected as count clock watch timer operable when f xt is selected as count clock operation stops watchdog timer operation stops a/d converter operation stops serial i/f operable at external sck can operation stops external interrupt (intp0 to intp4 and intkr) operable 379 chapter 20 standby function user?s manual u15251ee4v0ud00 (2) stop mode release the stop mode can be cleared with the following three types of sources. (a) release by unmasked interrupt request an unmasked interrupt request is used to release the stop mode. if interrupt acknowledge is enabled after the lapse of oscillati on stabilization time, vectored inte rrupt service is carried out. if interrupt acknowledge is disabled, the next address instruction is executed. figure 20-5: stop mode release by interrupt generation remark: the broken line indicates the case when the interrupt request which has cleared the standby status is acknowledged. stop instruction wait (time set by osts) oscillation stabilization wait status operating mode oscillation operationg mode stop mode oscillation stop oscillation standby release signal clock 380 chapter 20 standby function user?s manual u15251ee4v0ud00 (b) release by reset input the stop mode is cleare d and after the lapse of oscillation stabilization time, reset operation is carried out. figure 20-6: release by stop mode reset input remarks: 1. f x : main system clock oscillation frequency 2. values in parentheses apply to operation at f x = 8.0 mhz remark: x: don?t care table 20-4: operation after stop mode release release source mkxx prxx ie isp operation maskable interrupt request 0 0 0 x next address instruction execution 0 0 1 x interrupt service execution 0101 next address instruction execution 01x0 0 1 1 1 interrupt service execution 1 x x x stop mode hold reset input - - x x reset processing reset signal operating mode clock reset period stop mode oscillation stop oscillation stabilization wait status operating mode oscillation wait (2 17 /f x : 16.3 ms) stop instruction oscillation 381 user?s manual u15251ee4v0ud00 chapter 21 reset function 21.1 reset function the following three operations are available to generate the reset signal. external reset input with reset pin internal reset by watchdog timer overrun time detection internal reset by main clock failure detection. external reset and internal reset have no functional differences. in both cases, program execution starts at the address at 000 0h and 0001h by reset input. when a low level is input to the reset pin or the watchdog timer overflows, a reset is applied and each hardware is set to the status as shown in table 21-1. each pin has high impedance during reset input or during oscillation stabilization time just after reset clear. when a high level is input to the reset input, the reset is cleared and program execution starts after the lapse of oscillation stabilization time (2 17 /f x ). the reset applied by watchdog timer overflow is auto- matically cleared after a reset and program execution starts after the lapse of oscillation stabilization time (2 17 /f x ) (see figure 21-2, ?t iming of reset input by reset input,? on page 382, figure 21-3, ?tim- ing of reset due to watchdog timer overflow,? on page 382, and figure 21-4, ?timing of reset input in stop mode by reset input,? on page 382). cautions: 1. for an external reset, apply a low level for 10 s or more to the reset pin. 2. during reset the main system clock oscillation remains stopped but the sub- system clock oscillation continues. 3. when the stop mode is cleared by reset, the stop mode contents are held dur- ing reset. however, the port pin becomes high-impedance. figure 21-1: block diagram of reset function reset count clock reset control circuit watchdog timer stop over- flow reset signal interrupt function clock monitor main system clock subsystem clock 382 chapter 21 reset function user?s manual u15251ee4v0ud00 figure 21-2: timing of reset input by reset input figure 21-3: timing of reset due to watchdog timer overflow figure 21-4: timing of reset input in stop mode by reset input reset internal reset signal port pin delay delay high impedance x1 normal operation reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) x1 normal operation watchdog timer overflow internal reset signal port pin reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) high impedance reset internal reset signal port pin delay delay high impedance x1 normal operation normal operation (reset processing) stop instruction execution reset period (oscillation stop) oscillation stabilization time wait stop status (oscillation stop) 383 chapter 21 reset function user?s manual u15251ee4v0ud00 table 21-1: hardware status after reset (1/2) hardware status after reset program counter (pc) note 1 the contents of re set vector tables (0000h and 0001h) are set stack pointer (sp) undefined program status word (psw) 02h ram data memory undefined note 2 general register undefined note 2 lcd display data memory note 4 port (output latch) ports 0, 2, 4, 5, 6, 7 (p0, p2, p4, p5,p6, p7) 00h port mode register (pm0, pm 2, pm4, pm5, pm6, pm7) ffh pull-up resistor option register (pu0, pu2, pu4, pu5, pu6, pu7) 00h port function selection (pf2) 00h processor clock control register (pcc) 04h memory size switching register (ims) cfh internal expansion ram size switching register (ixs) note 3 oscillation stabilization time select register (osts) 04h 16-bit timer/event counter 0 timer register (tm0) 00h capture/compare register (cr00, cr01) 00h prescaler mode register (prm0) 00h mode control register (tmc0) 00h capture/compare control register 0 (crc0) 00h output control register (toc0) 00h 16-bit timer/event counter 2 timer register (tm2) 00h capture control register (cr20, cr21, cr22) 00h prescaler mode register (prm2) 00h mode control register (tmc2) 00h 8-bit timer/event counters 50 and 51 timer register (tm50, tm51) 00h compare register (cr50, cr51) 00h clock select register (tcl50, tcl51) 00h mode control register (tmc50, tmc51) 00h watch timer mode register (wtm) 00h watchdog timer clock selection register (wdcs) 00h mode register (wdtm) 00h pcl clock output clock output selection register (cks) 00h notes: 1. during reset input or oscillation stabilization time wait, only the pc contents among the hardware sta- tuses become undefined. all other hardware statuses remains unchanged after reset. 2. the post-reset status is held in the standby mode. 3. the value after reset depends on the product (see table 22-4, ?values when the internal expansion ram size switching register is reset,? on page 387) 384 chapter 21 reset function user?s manual u15251ee4v0ud00 serial interface operating mode register (csim20, csim30) 00h shift register (sio20, sio30) 00h serial interface switch register (sioswi) 00h serial receive data buffer (sirb20) 00h receive data buffer status (srbrs20) 00h asynchronous mode register (asim0) 00h asynchronous status register (asis0) 00h baudrate generator control register (brgr0) 00h transmit shift register (txs0) ffh receive buffer register (rxb0) a/d converter mode register (adm1) 00h conversion result register (adcr1) 00h input select register (ads1) 00h interrupt request flag register (if0l, if0h, if1l, if1h) 00h mask flag register (mk0l, mk0h, mk1l, mk1h) ffh priority specify flag register (pr0l, pr0h, pr1l, pr1h) ffh external interrupt rising edge register (egp) 00h external interrupt falling edge register (egn) 00h flash self-programming flash self-programming mode control register (flpmc) 08h self-programming and oscillation control reg- ister (spoc) 08h can control register (canc) 01h transmit control register (tcr) 00h receive message register (rmes) 00h redefinition register (redef) 00h error status register (canes) 00h transmit error counter register (tec) 00h receive error counter register (rec) 00h message count register (mcnt) 00h bit rate prescaler register (brprs) 3fh synchronous control register (sync0) 18h synchronous control register (sync1) 0eh mark control register (maskc) 00h counter register (smcnt) 00h pwm timer control register (mcntc) 00h main clock monitor clock moni tor mode register (clm) 00h key return input key return mode register (krm) 00h table 21-1: hardware status after reset (2/2) hardware status after reset 385 user?s manual u15251ee4v0ud00 chapter 22 pd78f0818 and memory definition the flash memory version of the pd780816 subseries includes the pd78f0818. the pd78f0818 replaces the internal mask rom of the pd780816 subseries with flash memory to which a program can be written, deleted and overwritten while mounted on the substrata. table 22-1 lists the differences among the pd78f0818 and the mask rom versions. caution: flash memory versions and mask rom versions differ in their noise tolerance and noise emission. if replacing flash memory versions with mask rom versions when changing from test production to mass production, be sure to perform sufficient evaluation with cs versions (not es versions) of mask rom versions. table 22-1: differences among pd78f0818 and mask rom versions item pd78f0818 mask rom versions ic pin none available v pp pin available none electrical characteristics please refer to chapter 24 ?electrical specifica- tions? on page 409 of this document. 386 chapter 22 pd78f0818 and memory definition user?s manual u15251ee4v0ud00 22.1 memory size switching register (ims) this register specifies the internal memory size by using the memory size switching register (ims), so that the same memory map as on the mask rom version can be achieved. ims is set with an 8-bit memory manipulation instruction. reset input sets this register to cfh. caution: when a device of the pd780816 subseries is selected, be sure to set the value spec- ified in table 22-2 to ims. other settings are prohibited. figure 22-1: memory size switching register format notes: 1. the values to be set after reset depend on the product (see table 22-2). 2. even if the flash version has a memory size of 59.5 k flash memory, the register has to be set to a flash memory size of 60 k. symbol76543210addressafter resetr/w ims ram2 ram1 ram0 0 rom3 rom2 rom1 rom0 fff0h cfh r/w rom3 rom2 rom1 rom0 internal rom size selection 1000 32 k bytes 1100 48 k bytes 1111 60 k bytes other than above setting prohibited ram2 ram1 ram0 internal high-speed ram size selection 110 1024 bytes other than above setting prohibited table 22-2: values to be set after reset of the memory size switching register part number reset value pd780814 c8h pd780816 cch pd78f0818 cfh 387 chapter 22 pd78f0818 and memory definition user?s manual u15251ee4v0ud00 22.2 internal expansion ram size switching register the pd78f0818 allows users to define its internal extension ram size by using the internal expansion ram size switching register (ixs), so that the same memory mapping as that of a mask rom version with a different internal expansion ram is possible. the ixs is set by an 8-bit memory manipulation instruction. reset signal input sets ixs to the value indicated in table 22-4. caution: when a device of the pd780816 subseries is selected, be sure to set the value spec- ified in table 22-3 to ixs. other settings are prohibited. figure 22-2: internal expansion ram si ze switching register (ixs) format notes: 1. the values after reset depend on the product (see table 22-4). 2. the value which is set in the ixs that has the identical memory map to the mask rom ver- sions is given in table 22-3. symbol76543210addressafter resetr/w ixs 0 0 0 0 ixram3 ixram2 ixram1 ixram0 fff4h note 1 w ixram3 ixram2 ixram1 ixram0 internal expansion ram capacity selection 1 0 1 1 480 bytes 1 0 0 0 2016 bytes other than above setting prohibited table 22-3: examples of internal expansion ram size switching register settings relevant mask rom version ixs setting pd780814 0bh pd780816 0bh pd78f0818 08h table 22-4: values when the internal expansion ram size switching register is reset part number reset value pd780814 0ch pd780816 0ch pd78f0818 08h 388 chapter 22 pd78f0818 and memory definition user?s manual u15251ee4v0ud00 22.3 self-programming and oscillation control register the pd78f0818 allows users to reduce the power consumption in halt mode by a selection of the clock supply of the flash memory. the spoc register is set with an 8-bit memory manipulation instruction. reset signal input sets spoc to 08h. figure 22-3: self-programming and oscillation control register (spoc) format caution: be sure to keep bits 2 to 7 = ?0?. after reset the read value of the spoc register will be 00h. symbol76543210addressafter resetr/w spoc000000hcsel1hcsel0ff51h08hr/w hcsel1 hcsel0 halt mode clock select 00 f x /2 4 (500 khz) 01 f x /2 5 (250 khz) 10 f x /2 6 (125 khz) 11 f x /2 7 (62.5 khz) 389 chapter 22 pd78f0818 and memory definition user?s manual u15251ee4v0ud00 22.4 flash memory programming with flash programmer on-board writing of flash memory (with device mounted on target system) is supported. on-board writing is done after connecting a dedicated flash writer to the host machine and the target system. moreover, writing to flash memory can also be performed using a flash memory writing adapter con- nected to flash programmer. 22.4.1 selection of transmission method writing to flash memory is performed using flash programmer and serial communication. select the transmission method for writing from table 22-5. for the selection of the transmission method, a format like the one shown in figure 22-4 is used. the transmission methods are selected with the v pp pulse numbers shown in table 22-5. cautions: 1. be sure to select the number of v pp pulses shown in table 22-5 for the transmis- sion method. 2. if performing write operations to fl ash memory with the uart transmission method, set the main system clock oscillation frequency to 3 mhz or higher. figure 22-4: transmission method selection format 22.4.2 initialization of the programming mode when v pp reaches up to 10 v with reset terminal activated, on-board programming mode becomes available. after release of reset , the programming mode is selected by the number of v pp pulses. table 22-5: transmission method list transmission method number of channels pin used number of v pp pulses 3-wire serial i/o (sio30) 1 si2/p20, so2/p21, sck2/p22 0 uart 1 rxd/p24, txd/p27 8 10 v v pp reset v dd v ss v dd v ss v pp pulses flash write mode 390 chapter 22 pd78f0818 and memory definition user?s manual u15251ee4v0ud00 22.4.3 flash memory programming function flash memory writing is performed through command and data transmit/receive operations using the selected transmission method. the main functions are listed in table 22-6. table 22-6: main functions of flash memory programming function description reset detects write stop and transmission synchronization chip verify compares the entire memory contents and input data chip internal verify compares the entire memory contents internally chip blank check checks the deletion status of the entire flash memory high-speed write performs writing to the flash memory according to the write start address and the number of write data (bytes) continuous write performs successive write operations using the data input with high- speed write operation chip pre-write performs the write operatio n with 00h to the entire flash memory area verify compares the entire flash area contents and input data area internal verify compares the entire flash area contents internally area erase erases the entire flash area area write back performs the write back fu nction after the erase of the flash area area blank check checks the deletion status of the entire flash area area pre-write performs the write operatio n with 00h to the entire flash area oscillation frequency setting inputs the re sonator oscillation frequency information erase time setting defines the flash memory erase time baudrate setting sets the transmission rate when the uart method is used write back time setting defines the flash memory write back time silicon signature read outputs the device name, memory capacity, and device block information 391 chapter 22 pd78f0818 and memory definition user?s manual u15251ee4v0ud00 22.4.4 flash programmer connection connection of flash programmer and pd78f0818 differs depending on communication method (3-wire serial i/o, uart). each case of connection shows in figures 22-5 and 22-6. figure 22-5: connection of usi ng the 3-wire sio30 method v pp v dd reset sck so si gnd v pp v dd reset sck2 si2 so2 v ss flash programmer pd78f0818 clk x1 392 chapter 22 pd78f0818 and memory definition user?s manual u15251ee4v0ud00 figure 22-6: connection of using the uart method v pp : programming voltage applied from the o-board programming tool. reset : a reset is generated and the device is set to the on-board programming mode. system clock : the cpu clock for the device clk may be supplied by the on-board program tool. clk, x1 : alternatively the crystal or ceramic o scillator on the target h/ w can be used in the on-board programming mode. the external system clock has to be connected with the x1 pin on the device. v dd : the power supply for the device may be supplied by the on-board program tool. alternatively the power supply on the target h/w can be used in the on-board programming mode. gnd : ground level v ss . sck2 : serial clock generated by the on-board programming tool. si2 : serial data sent by the on-board programming tool. so2 : serial data sent by the device. rxd : serial data sent by the on-board programming tool. txd : serial data sent by the device. 22.4.5 flash programming precautions please make sure that the signals used by the on-board programming tool do not conflict with other devices on the target h/w. a read functionality is not supported because of software protection. only a verify operation of the whole flash eprom is supported. in verify mode data from start address to final address has to be supplied by the programming tool. the device compares each data with on-chip flash content and replies with a signal for o.k. or not o.k. v pp v dd reset so si gnd v pp v dd reset rxd txd v ss flash programmer pd78f0818 clk x1 393 chapter 22 pd78f0818 and memory definition user?s manual u15251ee4v0ud00 22.5 flash self-programming control the pd78f0818 provides the secure self-programming with real-time support. further details are pro- vided in an application note (u14995e). 22.5.1 flash self-programming mode control register (flpmc) the flash programming mode control register allows to enable/disable the self-programming mode of the pd78f0818. the flpmc register is set with an 8-bit memory manipulation instruction. reset input sets flpmc to 08h. figure 22-7: flash self-programming mode control register format remark: the bit v pp is a read-only flag. symbol76543210addressafter resetr/w flpmc00001 v pp 0 flspm0 ff50h 08h r/w v pp programming voltage detected 0no 1yes flspm0 self-programming mode selection 0 normal operation mode 1 self-programming mode 394 user?s manual u15251ee4v0ud00 [memo] 395 user?s manual u15251ee4v0ud00 chapter 23 instruction set this chapter describes each instruction set of the pd780816 subseries as list table. for details of its operation and operation code, refer to the separate document ?78k/0 series user?s manual - instruction (u12326e) .? 23.1 legends used in operation list 23.1.1 operand identifiers and description methods operands are described in ?operand? column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). when there are two or more description methods, select one of them. alphabetic letters in capitals and symbols, #, !, $ and [ ] are key words and must be described as they are. each symbol has the following meaning. # : immediate data specification ! : absolute address specification $ : relative address specification [ ] : indirect address specification in the case of immediate data, describe an appropriate numeric value or a label. when using a label, be sure to describe the #, !, $, and [ ] symbols. for operand register identifiers, r and rp, either function names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1, r2, etc.) can be used for description. note: addresses from ffd0h to ffdfh cannot be accessed with these operands. remark: for special-function register symbols, refer to table 3-5, ?special function register list,? on page 62. table 23-1: operand identifiers and description methods identifier description method r x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) rp ax (rp0), bc (rp1), de (rp2), hl (rp3) sfr special-function register symbol note sfrp special-function register symbol (16-bit manipulatable register even addresses only) note saddr fe20h-ff1fh immediate data or labels saddrp fe20h-ff1fh immediate data or labels (even address only) addr16 0000h-ffffh immediate data or labels (only even addresses for 16-bit data transfer instructions) addr11 0800h-0fffh immediate data or labels addr5 0040h-007fh immediate data or labels (even address only) word 16-bit immediate data or label byte 8-bit immediate data or label bit 3-bit immediate data or label rbn rb0 to rb3 396 chapter 23 instruction set user?s manual u15251ee4v0ud00 23.1.2 description of ?operation? column a : a register; 8-bit accumulator x : x register b : b register c:c register d:d register e : e register h:h register l : l register ax : ax register pair; 16-bit accumulator bc : bc register pair de : de register pair hl : hl register pair pc : program counter sp : stack pointer psw : program status word cy : carry flag ac : auxiliary carry flag z:zero flag rbs : register bank select flag ie : interrupt request enable flag nmis : non-maskable interrupt servicing flag ( ) : memory contents indicated by address or register contents in parentheses x h , x l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) : exclusive logical sum (exclusive or) ?? : inverted data addr16 : 16-bit immediate data or label jdisp8 : signed 8-bit data (displacement value) 25.1.3 description of ?flag operation? column (blank) : not affected 0 : cleared to 0 1 : set to 1 x : set/cleared according to the result r : previously saved value is restored 397 chapter 23 instruction set user?s manual u15251ee4v0ud00 23.2 operation list table 23-2: operation list (1/8) instruction group mnemonic operands byte clock operation flag note 1 note 2 zaccy 8-bit data transfer mov r, #byte 2 4 - r m byte saddr, #byte 3 6 7 (saddr) m byte sfr, #byte 3 - 7 str m byte a, r note 3 12 -a m r r, a note 3 12 -r m a a, saddr 2 4 5 a m (saddr) saddr, a 2 4 5 (saddr) m a a, sfr 2 - 5 a m sfr sfr, a 2 - 5 sfr m a a, !addr16 3 8 9 + n a m (addr16) !addr16, a 3 8 9 + m (addr16) m a psw, #byte 3 - 7 psw m byte u u u a, psw 2 - 5 a m psw psw, a 2 - 5 psw m a u u u a, [de] 1 4 5 + n a m (de) [de], a 1 4 5 + m (de) m a a, [hl] 1 4 5 + n a m (hl) [hl], a 1 4 5 + m (hl) m a a, [hl + byte] 2 8 9 + n a m (hl + byte) [hl + byte], a 2 8 9 + m (hl + byte) m a a, [hl + b] 1 6 7 + n a m (hl + b) [hl + b], a 1 6 7 + m (hl + b) m a a, [hl + c] 1 6 7 + n a m hl + c) [hl + c], a 1 6 7 + m (hl + c) m a xch a, r note 3 12 -a l r a, saddr 2 4 6 a l (saddr) a, sfr 2 - 6 a l (sfr) a, !addr16 3 8 10+n+m a l (addr16) a, [de] 1 4 6+n+m a l (de) a, [hl] 1 4 6+n+m a l (hl) a, [hl + byte] 2 8 10+n+m a l (hl + byte) a, [hl + b] 2 8 10+n+m a l (hl + b) a, [hl + c] 2 8 10+n+m a l (hl + c) notes: 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed. 3. except ?r = a? 4. only when rp = bc, de or hl remarks: 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. 398 chapter 23 instruction set user?s manual u15251ee4v0ud00 16-bit data transfer movw rp, #word 3 6 - rp m word saddrp, #word 4 8 10 (saddrp) m word sfrp, #word 4 - 10 sfrp m word ax, saddrp 2 6 8 ax m (saddrp) saddrp, ax 2 6 8 (saddrp) m ax ax, sfrp 2 - 8 ax m sfrp sfrp, ax 2 - 8 sfrp m ax ax, rp note 4 1 4 - ax m rp rp, ax note 4 14 -rp m ax ax, !addr16 3 10 12 + 2n ax m (addr16) !addr16, ax 3 10 12 + 2m (addr16) m ax xchw ax, rp note 4 1 4 - ax u rp 8-bit operation add a, #byte 2 4 - a, cy m a + byte u u u saddr, #byte 3 6 8 (saddr), cy m (saddr) + byte u u u a, r note 3 24 -a, cy m a + r u u u r, a 2 4 - r, cy m r + a u u u a, saddr 2 4 5 a, cy m a + (saddr) u u u a, !addr16 3 8 9 + n a, cy m a + (addr16) u u u a, [hl] 1 4 5 + n a, cy m a + (hl) u u u a, [hl + byte] 2 8 9 + n a, cy m a + (hl + byte) u u u a, [hl + b] 2 8 9 + n a, cy m a + (hl + b) u u u a, [hl + c] 2 8 9 + n a, cy m a + (hl + c) u u u addc a, #byte 2 4 - a, cy m a + byte + cy u u u saddr, #byte 3 6 8 (saddr), cy m (saddr) + byte + cy u u u a, r note 3 24 -a, cy m a + r + cy u u u r, a 2 4 - r, cy m r + a + cy u u u a, saddr 2 4 5 a, cy m a + (saddr) + cy u u u a, !addr16 3 8 9 + n a, cy m a + (addr16) + cy u u u a, [hl] 1 4 5 + n a, cy m a + (hl) + cy u u u a, [hl + byte] 2 8 9 + n a, cy m a + (hl + byte) + cy u u u a, [hl + b] 2 8 9 + n a, cy m a + (hl + b) + cy u u u a, [hl + c] 2 8 9 + n a, cy m a + (hl + c) + cy u u u table 23-2: operation list (2/8) instruction group mnemonic operands byte clock operation flag note 1 note 2 zaccy notes: 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed. 3. except ?r = a? 4. only when rp = bc, de or hl remarks: 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. 399 chapter 23 instruction set user?s manual u15251ee4v0ud00 8-bit operation sub a, #byte 2 4 - a, cy m a - byte u u u saddr, #byte 3 6 8 (saddr), cy m (saddr) - byte u u u a, r note 3 24 -a, cy m a - r u u u r, a 2 4 - r, cy m r - a u u u a, saddr 2 4 5 a, cy m a - (saddr) u u u a, !addr16 3 8 9 + n a, cy m a - (addr16) u u u a, [hl] 1 4 5 + n a, cy m a - (hl) u u u a, [hl + byte] 2 8 9 + n a, cy m a - (hl + byte) u u u a, [hl + b] 2 8 9 + n a, cy m a - (hl + b) u u u a, [hl + c] 2 8 9 + n a, cy m a - (hl + c) u u u subc a, #byte 2 4 - a, cy m a - byte - cy u u u saddr, #byte 3 6 8 (saddr), cy m (saddr) - byte - cy u u u a, r note 3 24 -a, cy m a - r - cy u u u r, a 2 4 - r, cy m r - a - cy u u u a, saddr 2 4 5 a, cy m a - (saddr) - cy u u u a, !addr16 3 8 9 + n a, cy m a - (addr16) - cy u u u a, [hl] 1 4 5 + n a, cy m a - (hl) - cy u u u a, [hl + byte] 2 8 9 + n a, cy m a - (hl + byte) - cy u u u a, [hl + b] 2 8 9 + n a, cy m a - (hl + b) - cy u u u a, [hl + c] 2 8 9 + n a, cy m a - (hl + c) - cy u u u and a, #byte 2 4 - a m a ? byte u saddr, #byte 3 6 8 (saddr) m (saddr) ? byte u a, r note 3 24 -a m a ? r u r, a 2 4 - r m r ? a u a, saddr 2 4 5 a m a ? (saddr) u a, !addr16 3 8 9 + n a m a ? (addr16) u a, [hl] 1 4 5 + n a m a ? (hl) u a, [hl + byte] 2 8 9 + n a m a ? (hl + byte) u a, [hl + b] 2 8 9 + n a m a ? (hl + b) u a, [hl + c] 2 8 9 + n a m a ? (hl + c) u table 23-2: operation list (3/8) instruction group mnemonic operands byte clock operation flag note 1 note 2 zaccy notes: 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed. 3. except ?r = a? 4. only when rp = bc, de or hl remarks: 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. 400 chapter 23 instruction set user?s manual u15251ee4v0ud00 8-bit operation or a, #byte 2 4 - a m a ? byte u saddr, #byte 3 6 8 (saddr) m (saddr) ? byte u a, r note 3 24 -a m a ? r u r, a 2 4 - r m r ? a u a, saddr 2 4 5 a m a ? (saddr) u a, !addr16 3 8 9 + n a m a ? (addr16) u a, [hl] 1 4 5 + n a m a ? (hl) u a, [hl + byte] 2 8 9 + n a m a ? (hl + byte) u a, [hl + b] 2 8 9 + n a m a ? (hl + b) u a, [hl + c] 2 8 9 + n a m a ? (hl + c) u xor a, #byte 2 4 - a m a ? byte u saddr, #byte 3 6 8 (saddr) m (saddr) ? byte u a, r note 3 24 -a m a ? r u r, a 2 4 - r m r ? a u a, saddr 2 4 5 a m a ? (saddr) u a, !addr16 3 8 9 + n a m a ? (addr16) u a, [hl] 1 4 5 + n a m a ? (hl) u a, [hl + byte] 2 8 9 + n a m a ? (hl + byte) u a, [hl + b] 2 8 9 + n a m a ? (hl + b) u a, [hl + c] 2 8 9 + n a m a ? (hl + c) u cmp a, #byte 2 4 - a - byte u u u saddr, #byte 3 6 8 (saddr) - byte u u u a, r note 3 2 4 - aa - r u u u r, a 2 4 - r - a u u u a, saddr 2 4 5 a - (saddr) u u u a, !addr16 3 8 9 + n a - (addr16) u u u a, [hl] 1 4 5 + n a - (hl) u u u a, [hl + byte] 2 8 9 + n a - (hl + byte) u u u a, [hl + b] 2 8 9 + n a - (hl + b) u u u a, [hl + c] 2 8 9 + n a - (hl + c) u u u 16-bit operation addw ax, #word 3 6 - ax, cy m ax + word u u u subw ax, #word 3 6 - ax, cy m ax - word u u u cmpw ax, #word 3 6 - ax ? word u u u multiply/ divide mulu x 2 16 - ax m a x x divuw c 2 25 - ax (quotient), c (remainder) m ax c table 23-2: operation list (4/8) instruction group mnemonic operands byte clock operation flag note 1 note 2 zaccy notes: 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed. 3. except ?r = a? 4. only when rp = bc, de or hl remarks: 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. 401 chapter 23 instruction set user?s manual u15251ee4v0ud00 increment/ decrement inc r12-r m r + 1 u u saddr 2 4 6 (saddr) m (saddr) + 1 u u dec r12-r m r ? 1 u u saddr 2 4 6 (saddr) m (saddr) ? 1 u u incw rp 1 4 - rp m rp + 1 decw rp 1 4 - rp m rp - 1 rotate ror a, 1 1 2 - (cy, a 7 m a 0 , a m ? 1 m a m ) x 1 time u rol a, 1 1 2 - (cy, a 0 m a 7 , a m + 1 m a m ) x 1 time u rorc a, 1 1 2 - (cy m a 0 , a 7 m cy, a m ? 1 m a m ) x 1 time u rolc a, 1 1 2 - (cy m a 7 , a 0 m cy, a m + 1 m a m ) x 1 time u ror4 [hl] 2 10 12+n+m a 3 ? 0 m (hl) 3 ? 0 , (hl) 7 ? 4 m a 3 ? 0 , (hl) 3 ? 0 m (hl) 7 ? 4 rol4 [hl] a 3 ? 0 m (hl) 7 ? 4 , (hl) 3 ? 0 m a 3 ? 0 , (hl) 7 ? 4 m (hl) 3 ? 0 bcd adjust adjba 2 4 - decimal adjust accumulator after addition u u u adjbs 2 4 - decimal adjust accumulator after sub- tract u u u bit manipulate mov1 cy, saddr.bit 3 6 7 cy m saddr.bit) u cy, sfr.bit 3 - 7 cy m sfr.bit u cy, a.bit 2 4 - cy m a.bit u cy, psw.bit 3 - 7 cy m psw.bit u cy, [hl].bit 2 6 7 + n cy m (hl).bit u saddr.bit, cy 3 6 8 (saddr.bit) m cy sfr.bit, cy 3 - 8 sfr.bit m cy a.bit, cy 2 4 - a.bit m cy psw.bit, cy 3 - 8 psw.bit m cy u u [hl].bit, cy 2 6 8+n+m (hl).bit m cy and1 cy, saddr.bit 3 6 7 cy m cy ? saddr.bit) u cy, sfr.bit 3 - 7 cy m cy ? sfr.bit u cy, a.bit 2 4 - cy m cy ? a.bit u cy, psw.bit 3 - 7 cy m cy ? psw.bit u cy, [hl].bit 2 6 7 + n cy m cy ? (hl).bit u table 23-2: operation list (5/8) instruction group mnemonic operands byte clock operation flag note 1 note 2 zaccy notes: 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed. 3. except ?r = a? 4. only when rp = bc, de or hl remarks: 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. 402 chapter 23 instruction set user?s manual u15251ee4v0ud00 bit manipulate or1 cy, saddr.bit 3 6 7 cy m cy ? saddr.bit) u cy, sfr.bit 3 - 7 cy m cy ? sfr.bit u cy, a.bit 2 4 - cy m cy ? a.bit u cy, psw.bit 3 - 7 cy m cy ? psw.bit u cy, [hl].bit 2 6 7 + n cy m cy ? (hl).bit u xor1 cy, saddr.bit 3 6 7 cy m cy ? saddr.bit) u cy, sfr.bit 3 - 7 cy m cy ? sfr.bit u cy, a.bit 2 4 - cy m cy ? a.bit u cy, psw.bit 3 - 7 cy m cy ? psw.bit u cy, [hl].bit 2 6 7 + n cy m cy ? (hl).bit u set1 saddr.bit 2 4 6 (saddr.bit) m 1 sfr.bit 3 - 8 sfr.bit m 1 a.bit 2 4 - a.bit m 1 psw.bit 2 - 6 psw.bit m 1 u u u [hl].bit 2 6 8+n+m (hl).bit m 1 clr1 saddr.bit 2 4 6 (saddr.bit) m 0 sfr.bit 3 - 8 sfr.bit m 0 a.bit 2 4 - a.bit m 0 psw.bit 2 - 6 psw.bit m 0 u u u [hl].bit 2 6 8+n+m (hl).bit m 0 set1 cy 1 2 - cy m 11 clr1 cy 1 2 - cy m 00 not1 cy 1 2 - cy m cy u table 23-2: operation list (6/8) instruction group mnemonic operands byte clock operation flag note 1 note 2 zaccy notes: 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed. 3. except ?r = a? 4. only when rp = bc, de or hl remarks: 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. 403 chapter 23 instruction set user?s manual u15251ee4v0ud00 call/return call !addr16 3 7 - (sp ? 1) m (pc + 3) h , (sp ? 2) m (pc + 3) l , pc m addr16, sp m sp ? 2 callf !addr11 2 5 - (sp ? 1) m (pc + 2) h , (sp ? 2) m (pc + 2) l , pc 15 ? 11 m 00001, pc 10 ? 0 m addr11, sp m sp ? 2 callt [addr5] 1 6 - (sp ? 1) m (pc + 1) h , (sp ? 2) m (pc + 1) l , pc h m (00000000, addr5 + 1), pc l m (00000000, addr5), sp m sp ? 2 brk 1 6 - (sp ? 1) m psw, (sp ? 2) m (pc + 1) h , (sp ? 3) m (pc + 1) l , pch m (003fh), pcl m (003eh), sp m sp ? 3, ie m 0 ret 1 6 - pc h m (sp + 1), pc l m (sp),sp m sp + 2 reti 1 6 - pc h m (sp + 1), pc l m (sp), psw m (sp + 2), sp m sp + 3, nmis m 0 rrr retb 1 6 - pch m (sp + 1), pcl m (sp), psw m (sp + 2), sp m sp + 3 rrr stack manipulate push psw 1 2 - (sp ? 1) m psw, sp m sp ? 1 rp 1 4 - (sp ? 1) m rp h , (sp ? 2) m rp l , sp m sp ? 2 pop psw 1 2 - psw m (sp), sp m sp + 1 r r r rp 1 4 - rp h m (sp + 1), rp l m (sp), sp m sp + 2 movw sp, #word 4 - 10 sp m word sp, ax 2 - 8 sp m ax ax, sp 2 - 8 ax m sp uncondi- tional branch br !addr16 3 6 - pc m addr16 $addr16 2 6 - pc m pc + 2 + jdisp8 ax 2 8 - pc h m a, pcl m x condi- tional branch bc $addr16 2 6 - pc m pc + 2 + jdisp8 if cy = 1 bnc $addr16 2 6 - pc m pc + 2 + jdisp8 if cy = 0 bz $addr16 2 6 - pc m pc + 2 + jdisp8 if z = 1 bnz $addr16 2 6 - pc m pc + 2 + jdisp8 if z = 0 table 23-2: operation list (7/8) instruction group mnemonic operands byte clock operation flag note 1 note 2 zaccy notes: 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed. 3. except ?r = a? 4. only when rp = bc, de or hl remarks: 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. 404 chapter 23 instruction set user?s manual u15251ee4v0ud00 condi- tional branch bt saddr.bit, $addr16 3 8 9 pc m pc + 3 + jdisp8 if(saddr.bit) = 1 sfr.bit, $addr16 4 - 11 pc m pc + 4 + jdisp8 if sfr.bit = 1 a.bit, $addr16 3 8 - pc m pc + 3 + jdisp8 if a.bit = 1 psw.bit, $addr16 3 - 9 pc m pc + 3 + jdisp8 if psw.bit = 1 [hl].bit, $addr16 3 10 11 + n pc m pc + 3 + jdisp8 if (hl).bit = 1 bf saddr.bit, $addr16 4 10 11 pc m pc + 4 + jdisp8 if(saddr.bit) = 0 sfr.bit, $addr16 4 - 11 pc m pc + 4 + jdisp8 if sfr.bit = 0 a.bit, $addr16 3 8 - pc m pc + 3 + jdisp8 if a.bit = 0 psw.bit, $addr16 4 - 11 pc m pc + 4 + jdisp8 if psw. bit = 0 [hl].bit, $addr16 3 10 11 + n pc m pc + 3 + jdisp8 if (hl).bit = 0 btclr saddr.bit, $addr16 4 10 12 pc m pc + 4 + jdisp8 if(saddr.bit) = 1 then reset(saddr.bit) sfr.bit, $addr16 4 - 12 pc m pc + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit a.bit, $addr16 3 8 - pc m pc + 3 + jdisp8 if a.bit = 1 then reset a.bit psw.bit, $addr16 4 - 12 pc m pc + 4 + jdisp8 if psw.bit = 1 then reset psw.bit u u u [hl].bit, $addr16 3 10 12+n+m pc m pc + 3 + jdisp8 if (hl).bit = 1 then reset (hl).bit dbnz b, $addr16 2 6 - b m b ? 1, then pc m pc + 2 + jdisp8 if b z 0 c, $addr16 2 6 - c m c ?1, then pc m pc + 2 + jdisp8 if c z 0 saddr. $addr16 3 8 10 (saddr) m (saddr) ? 1, then pc m pc + 3 + jdisp8 if(saddr) z 0 cpu control sel rbn 2 4 - rbs1, 0 m n nop 1 2 - no operation ei 2 - 6 ie m 1(enable interrupt) di 2 - 6 ie m 0(disable interrupt) halt 2 6 - set halt mode stop 2 6 - set stop mode table 23-2: operation list (8/8) instruction group mnemonic operands byte clock operation flag note 1 note 2 zaccy notes: 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed. 3. except ?r = a? 4. only when rp = bc, de or hl remarks: 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. 405 chapter 23 instruction set user?s manual u15251ee4v0ud00 23.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz note: except r = a table 23-3: 8-bit instructions 2nd operand #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + byte] [hl + b] [hl + c] $addr16 1 none 1st operand a add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp ror rol rorc rolc rmov mov add addc sub subc and or xor cmp inc dec b, c dbnz sfr mov mov saddr mov add addc sub subc and or xor cmp dbnz inc dec !addr16 mov psw mov mov push pop [de] mov [hl] mov ror4 rol4 [hl + byte] [hl + b] [hl + c] mov x mulu c divu w 406 chapter 23 instruction set user?s manual u15251ee4v0ud00 (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw note: only when rp = bc, de, hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr table 23-4: 16-bit instructions 2nd operand #word ax rp note sfrp saddrp !addr16 sp none 1st operand ax addw subw cmpw movw xchw movw movw movw movw rp movw movw note incw decw push pop sfrp movw movw saddrp movw movw !addr16 movw sp movw movw table 23-5: bit manipulation instructions 2nd operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none 1st operand a.bit mov1 bt bf btclr set1 clr1 sfr.bit mov1 bt bf btclr set1 clr1 saddr.bit mov1 bt bf btclr set1 clr1 psw.bit mov1 bt bf btclr set1 clr1 [hl].bit mov1 bt bf btclr set1 clr1 cy mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 set1 clr1 not1 407 chapter 23 instruction set user?s manual u15251ee4v0ud00 (4) call/instructions/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop table 23-6: call/instructions/branch instructions 2nd operand ax !addr16 !addr11 [addr5] $addr16 1st operand basic instruction br call br callf callt br bc bnc bz bnz compound instruction bt bf btclr dbnz 408 user?s manual u15251ee4v0ud00 [memo] 409 user?s manual u15251ee4v0ud00 chapter 24 electric al specifications 24.1 absolute maximum ratings (1) pd780814(a), pd780816(a), pd78f0818(a) (t a = 25c) note: effective value should be calculated as follows: [effective value] = [peak value] u ? duty caution: product quality may suffer if the absolute maximum ratings are exceeded for even a single parameter or even momentarily. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. remark: the characteristics of the dual-function pins are the same as those of the port pins unless otherwise specified. parameter symbol conditions rating unit supply voltage v dd -0.3 to + 6.0 v v pp pd78f0818(a) -0.3 to + 11.0 av dd / av ref av dd / av ref = v dd -0.3 to v dd + 0.3 av ss -0.3 to + 0.3 input voltage v i1 p00 - p03, p20 - p27, p40 - p47, p50 - p57, p60 - p67, p70, p71, x1, x2, cl1, reset , crxd -0.3 to v dd +0.3 output voltage v o -0.3 to v dd +0.3 analog input voltage v an p10 to p17, ani8 to ani11 analog input pin av ss -0.3 to av dd +0.3 high level output current i oh 1 pin -10 ma p00 - p03, p20 - p27, p40 - p47, p50 - p57, p60 - p67, p70, p71, ctxd total -20 low level output current i ol note 1 pin peak 20 effective 10 p00 - p03, p20 - p27, p40 - p47, p50 - p57, p60 - p67, p70, p71, ctxd total peak 50 effective 25 operating ambient temperature t opt -40 to +85 q c storage temperature t stg pd780814(a) and pd780816(a) -65 to +150 pd78f0818(a) -40 to +125 410 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 (2) pd780814(a1), pd780816(a1) (t a = 25c) these specifications are only target values and may not be satisfied by mass-produced products. note: effective value should be calculated as follows: [effective value] = [peak value] u ? duty caution: product quality may suffer if the absolute maximum ratings are exceeded for even a single parameter or even momentarily. tha t is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. remark: the characteristics of the dual-function pins ar e the same as those of the port pins unless otherwise specified. parameter symbol conditions rating unit supply voltage v dd -0.3 to + 6.0 v av dd / av ref av dd / av ref = v dd -0.3 to v dd + 0.3 av ss -0.3 to + 0.3 input voltage v i1 p00 - p03, p20 - p27, p40 - p47, p50 - p57, p60 - p67, p70, p71, x1, x2, cl1, reset , crxd -0.3 to v dd +0.3 output voltage v o -0.3 to v dd +0.3 analog input voltage v an p10 to p17, ani8 to ani11 analog input pin av ss -0.3 to av dd +0.3 high level output current i oh 1 pin -10 ma p00 - p03, p20 - p27, p40 - p47, p50 - p57, p60 - p67, p70, p71, ctxd total -20 low level output current i ol note 1 pin peak 20 effective 10 p00 - p03, p20 - p27, p40 - p47, p50 - p57, p60 - p67, p70, p71, ctxd total peak 50 effective 25 operating ambient temperature t opt -40 to +110 q c storage temperature t stg -65 to +150 411 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 (3) pd780814(a2), pd780816(a2) (t a = 25c) note: effective value should be calculated as follows: [effective value] = [peak value] u ? duty caution: product quality may suffer if the absolute maximum ratings are exceeded for even a single parameter or even momentarily. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. remark: the characteristics of the dual-function pins are the same as those of the port pins unless otherwise specified. parameter symbol conditions rating unit supply voltage v dd -0.3 to + 6.0 v av dd / av ref av dd / av ref = v dd -0.3 to v dd + 0.3 av ss -0.3 to + 0.3 input voltage v i1 p00 - p03, p20 - p27, p40 - p47, p50 - p57, p60 - p67, p70, p71, x1, x2, cl1, reset , crxd -0.3 to v dd +0.3 output voltage v o -0.3 to v dd +0.3 analog input voltage v an p10 to p17, ani8 to ani11 analog input pin av ss -0.3 to av dd +0.3 high level output current i oh 1 pin -10 ma p00 - p03, p20 - p27, p40 - p47, p50 - p57, p60 - p67, p70, p71, ctxd total -20 low level output current i ol note 1 pin peak 20 effective 10 p00 - p03, p20 - p27, p40 - p47, p50 - p57, p60 - p67, p70, p71, ctxd total peak 50 effective 25 operating ambient temperature t opt -40 to +125 q c storage temperature t stg -65 to +150 412 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 24.2 capacitance (1) pd780814(a), pd780816(a), pd78f0818(a) (t a = 25c, v dd = v ss = 0 v) remark: the characteristics of the dual-function pins ar e the same as those of the port pins unless otherwise specified. (2) pd780814(a1), pd780816(a1) (t a = 25c, v dd = v ss = 0 v) these specifications are only target values and may not be satisfied by mass-produced products. remark: the characteristics of the dual-function pins ar e the same as those of the port pins unless otherwise specified. (3) pd780814(a2), pd780816(a2) (t a = 25c, v dd = v ss = 0 v) remark: the characteristics of the dual-function pins ar e the same as those of the port pins unless otherwise specified. parameter symbol function min. typ. max. unit input capacitance c in f = 1 mhz other than measured pins: 0 v 15 pf input/output capacitance c io f = 1 mhz other than measured pins: 0 v p00 - p03, p20 - p27, p40 - p47, p50 - p57, p60 - p67, p70, p71 15 pf parameter symbol function min. typ. max. unit input capacitance c in f = 1 mhz other than measured pins: 0 v 15 pf input/output capacitance c io f = 1 mhz other than measured pins: 0 v p00 - p03, p20 - p27, p40 - p47, p50 - p57, p60 - p67, p70, p71 15 pf parameter symbol function min. typ. max. unit input capacitance c in f = 1 mhz other than measured pins: 0 v 15 pf input/output capacitance c io f = 1 mhz other than measured pins: 0 v p00 - p03, p20 - p27, p40 - p47, p50 - p57, p60 - p67, p70, p71 15 pf 413 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 24.3 main system clock oscillation circuit characteristics (1) pd780814(a), pd780816(a), pd78f0818(a) (t a = -40c to +85c, v dd = 4.0 to 5.5 v) notes: 1. indicates only oscillation circui t characteristics. refer to ?ac characteristics? for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. cautions: 1. when using the main system clock oscillation circuit, wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. wiring should be as short as possible. wiring should not cross other signal lines. wiring should not be placed close to a varying high current. the potential of the oscillation circ uit capacitor ground should always be the same as that of v ss . do not ground wiring to a ground pattern in which a high current flows. do not fetch a signal from the oscillation circuit. 2. when the main system clock is stopped and the system is operated by the sub- system clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program. resonator recommended circuit parameter conditions min. typ. max. unit ceramic resonator oscillator frequency (f x ) note 1 v dd = 4.0 to 5.5 v 4.0 8.0 8.38 mhz oscillation stabiliza- tion time note 2 after v dd reaches oscillator voltage range min. 4.0 v 10 ms crystal resonator oscillator frequency (f x ) note 1 v dd = 4.0 to 5.5 v 4.0 8.0 8.38 mhz oscillation stabiliza- tion time note 2 after v dd reaches oscillator voltage range min. 4.0 v 10 ms external clock x1 input frequency (f x ) note 1 v dd = 4.0 to 5.5 v 4.0 8.0 8.38 mhz x1 input high/low-level width (t xh , t xl ) v dd = 4.0 to 5.5 v 55 125 ns ic x2 x1 c2 c1 ic x2 x1 c2 c1 x2 x1 pd74hcu04 open 414 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 (2) pd780814(a1), pd780816(a1) (t a = -40c to +110c, v dd = 4.0 to 5.5 v) these specifications are only target values and may not be satisfied by mass-produced products. notes: 1. indicates only oscillation circuit characteristics. refer to ?ac characteristics? for instruction execution time. 2. time required to stabilize oscillation after reset or st op mode release. cautions: 1. when using the main system clock os cillation circuit, wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. wiring should be as short as possible. wiring should not cross other signal lines. wiring should not be placed close to a varying high current. the potential of the oscillation circuit capacitor ground should always be the same as that of v ss . do not ground wiring to a ground pattern in which a high current flows. do not fetch a signal from the oscillation circuit. 2. when the main system clock is stopped and the system is operated by the sub- system clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program. resonator recommended circuit parameter conditions min. typ. max. unit ceramic resonator oscillator frequency (f x ) note 1 v dd = 4.0 to 5.5 v 4.0 8.0 8.38 mhz oscillation stabiliza- tion time note 2 after v dd reaches oscillator voltage range min. 4.0 v 10 ms crystal resonator oscillator frequency (f x ) note 1 v dd = 4.0 to 5.5 v 4.0 8.0 8.38 mhz oscillation stabiliza- tion time note 2 after v dd reaches oscillator voltage range min. 4.0 v 10 ms external clock x1 input frequency (f x ) note 1 v dd = 4.0 to 5.5 v 4.0 8.0 8.38 mhz x1 input high/low-level width (t xh , t xl ) v dd = 4.0 to 5.5 v 55 125 ns ic x2 x1 c2 c1 ic x2 x1 c2 c1 x2 x1 pd74hcu04 open 415 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 (3) pd780814(a2), pd780816(a2) (t a = -40c to +125c, v dd = 4.0 to 5.5 v) notes: 1. indicates only oscillation circui t characteristics. refer to ?ac characteristics? for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. cautions: 1. when using the main system clock oscillation circuit, wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. wiring should be as short as possible. wiring should not cross other signal lines. wiring should not be placed close to a varying high current. the potential of the oscillation circ uit capacitor ground should always be the same as that of v ss . do not ground wiring to a ground pattern in which a high current flows. do not fetch a signal from the oscillation circuit. 2. when the main system clock is stopped and the system is operated by the sub- system clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program. resonator recommended circuit parameter conditions min. typ. max. unit ceramic resonator oscillator frequency (f x ) note 1 v dd = 4.0 to 5.5 v 4.0 8.0 8.38 mhz oscillation stabiliza- tion time note 2 after v dd reaches oscillator voltage range min. 4.0 v 10 ms crystal resonator oscillator frequency (f x ) note 1 v dd = 4.0 to 5.5 v 4.0 8.0 8.38 mhz oscillation stabiliza- tion time note 2 after v dd reaches oscillator voltage range min. 4.0 v 10 ms external clock x1 input frequency (f x ) note 1 v dd = 4.0 to 5.5 v 4.0 8.0 8.38 mhz x1 input high/low-level width (t xh , t xl ) v dd = 4.0 to 5.5 v 55 125 ns ic x2 x1 c2 c1 ic x2 x1 c2 c1 x2 x1 pd74hcu04 open 416 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 24.4 subsystem clock oscillation circuit characteristics (1) pd780814(a), pd780816(a), pd78f0818(a) (t a = -40c to +85c, v dd = 4.0 to 5.5 v) notes: 1. only oscillator circuit characteristics are show n. regarding instruction execute time, please refer to ac characteristics. 2. the input frequency of 8.00 mhz to cl1 is only valid as frequency input to the dcan. cautions: 1. when using the subsystem clock osci llation circuit, wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. wiring should be as short as possible. wiring should not cross other signal lines. wiring should not be placed close to a varying high current. the potential of the oscillation circuit capacitor ground should always be the same as that of v ss . do not ground wiring to a ground pattern in which a high current flows. do not fetch a signal from the oscillation circuit. 2. the subsystem clock oscillation circuit is designed to be a circuit with a low amplification level, for low power consum ption more prone to mis-operation due to noise than that of the main system clock. therefore, when using the sub- system clock, take special cautions for wiring methods. resonator recommended circuit parameter test conditions min. typ. max. unit rc osc. note 1 oscillator frequency (f xt ) 4.0 v d v dd d 5.5 v r = 300 k : c = 33 pf 32 40 100 khz external clock note 1 cl1 input note 2 frequency (f xt ) 4.0 v d v dd d 5.5 v 0.032 8.0 8.38 mhz cl1 input high/low level width (t xth , t xtl ) 4.0 v d v dd d 5.5 v 0.055 15.6 s r cl1 cl2 c cl1 cl2 417 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 (2) pd780814(a1), pd780816(a1) (t a = -40c to +110c, v dd = 4.0 to 5.5 v) these specifications are only target values and may not be satisfied by mass-produced products. notes: 1. only oscillator circuit characteristics are show n. regarding instructio n execute time, please refer to ac characteristics. 2. the input frequency of 8.00 mhz to cl1 is only valid as frequency input to the dcan. cautions: 1. when using the subsystem clock os cillation circuit, wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. wiring should be as short as possible. wiring should not cross other signal lines. wiring should not be placed close to a varying high current. the potential of the oscillation circ uit capacitor ground should always be the same as that of v ss . do not ground wiring to a ground pattern in which a high current flows. do not fetch a signal from the oscillation circuit. 2. the subsystem clock oscillation circuit is designed to be a circuit with a low amplification level, for low power consumption more prone to mis-operation due to noise than that of the main system clock. therefore, when using the sub- system clock, take special cautions for wiring methods. resonator recommended circuit parameter test conditions min. typ. max. unit rc osc. note 1 oscillator frequency (f xt ) 4.0 v d v dd d 5.5 v r = 300 k : c = 33 pf 32 40 100 khz external clock note 1 cl1 input note 2 frequency (f xt ) 4.0 v d v dd d 5.5 v 0.032 8.0 8.38 mhz cl1 input high/low level width (t xth , t xtl ) 4.0 v d v dd d 5.5 v 0.055 15.6 s r cl1 cl2 c cl1 cl2 418 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 (3) pd780814(a2), pd780816(a2) (t a = -40c to +125c, v dd = 4.0 to 5.5 v) notes: 1. only oscillator circuit characteristics are show n. regarding instruction execute time, please refer to ac characteristics. 2. the input frequency of 8.00 mhz to cl1 is only valid as frequency input to the dcan. cautions: 1. when using the subsystem clock osci llation circuit, wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. wiring should be as short as possible. wiring should not cross other signal lines. wiring should not be placed close to a varying high current. the potential of the oscillation circuit capacitor ground should always be the same as that of v ss . do not ground wiring to a ground pattern in which a high current flows. do not fetch a signal from the oscillation circuit. 2. the subsystem clock oscillation circuit is designed to be a circuit with a low amplification level, for low power consum ption more prone to mis-operation due to noise than that of the main system clock. therefore, when using the sub- system clock, take special cautions for wiring methods. resonator recommended circuit parameter test conditions min. typ. max. unit rc osc. note 1 oscillator frequency (f xt ) 4.0 v d v dd d 5.5 v r = 300 k : c = 33 pf 32 40 100 khz external clock note 1 cl1 input note 2 frequency (f xt ) 4.0 v d v dd d 5.5 v 0.032 8.0 8.38 mhz cl1 input high/low level width (t xth , t xtl ) 4.0 v d v dd d 5.5 v 0.055 15.6 s r cl1 cl2 c cl1 cl2 419 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 24.5 dc characteristics (1) pd780814(a), pd780816(a), pd78f0818(a) (t a = -40c to +85c, v dd = 4.0 to 5.5 v) remark: the characteristics of the dual-function pins are the same as those of the port pins unless otherwise specified. parameter symbol conditions min. typ. max. unit high-level input voltage v ih1 p00 - p03, p10 - p17, p20 - p27, p40 - p47, p50 - p57, p60 - p67, p70, p71, crxd, ani0 - ani11 0.7 v dd v dd v v ih2 reset 0.8 v dd v dd v ih4 x1, x2, cl1 v dd - 0.5 v dd low-level input voltage v il1 p00 - p03, p10 - p17, p20 - p27, p40 - p47, p50 - p57, p60 - p67, p70, p71, crxd, ani0 - ani11 0 0.3 v dd v il2 reset 0 0.2 v dd v il4 x1, x2, cl1 0 0.4 high-level output voltage v oh1 p00 - p03, p10 - p17, p20 - p27, p40 - p47, p50 - p57, p60 - p67, p70, p71, ctxd v dd = 4.0 - 5.5 v i oh = -1 ma v dd - 1.0 v dd low-level output voltage v ol1 p00 - p03, p10 - p17, p20 - p27, p40 - p47, p50 - p57, p60 - p67, p70, p71, ctxd v dd = 4.0 - 5.5 v i ol = 1.6 ma 00.4 high-level input leakage current i lih1 p00 - p03, p10 - p17, p20 - p27, p40 - p47, p50 - p57, p60 - p67, p70, p71, reset , crxd, ani0 - ani11 v in = v dd 03 a i lih2 x1, x2, cl1, cl2 0 20 low-level input leakage current i lil1 p00 - p03, p10 - p17, p20 - p27, p40 - p47, p50 - p57, p60 - p67, p70, p71, reset , crxd, ani0 - ani11 v in = 0 v 0-3 ii lil2 x1, x2, cl1, cl2 0 -20 high-level output leakage current i loh v out = v dd 03 low-level output leakage current i lol v out = 0 v 0-3 software pull-up resistor r2 v in = 0 v 4.5 v d v dd d 5.5 v 10 30 100 k : 420 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 (2) pd780814(a), pd780816(a) (t a = -40c to +85c, v dd = 4.0 to 5.5 v) mask rom version notes: 1. current through v dd0 , v dd1 respectively through v ss0 , v ss1 . excluded is the current through the inside pull-up resistors, through av dd /av ref , the port current. 2. cpu is operable. the other peripherals like: can controller, timer 0, timer 2, serial interfaces, a/d converter etc. are stopped. 3. cpu and all peripherals (except for the a/d converter) are in operating mode and pcl out- put is f x . remarks: 1. f x : main system clock oscillation frequency. 2. f xt : subsystem clock oscillation frequency. 3. the typical values are with respect to t a = 25c. parameter symbol test conditions min. typ. max. unit power supply current note 1 i dd1 f x = 8 mhz, crystal/ceramic oscillation operating mode (pcc = 00h) note 2 5.5 11 ma f x = 8 mhz, crystal/ceramic oscillation operating mode (pcc = 00h) note 3 9.5 19 i dd3 rc oscillation operating mode (f xt = 40 khz) 150 500 a i dd4 rc oscillation halt mode (f xt = 40 khz) 60 180 i dd5 cl1 = v dd stop mode 130 421 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 (3) pd78f0818(a) (t a = -40c to +85c, v dd = 4.0 to 5.5 v) flash eeprom version notes: 1. current through v dd0 , v dd1 respectively through v ss0 , v ss1 . excluded is the current through the inside pull-up resistors, through av dd /av ref , the port current. 2. cpu is operable. the other peripherals like: can controller, timer 0, timer 2, serial interfaces, a/d converter etc. are stopped. 3. cpu and all peripherals (except for the a/d converter) are in operating mode and pcl out- put is f x . remarks: 1. f x : main system clock oscillation frequency. 2. f xt : subsystem clock oscillation frequency. 3. the typical values are with respect to t a = 25c. parameter symbol test conditions min. typ. max. unit power supply current note 1 i dd1 f x = 8 mhz, crystal/ceramic oscillation operating mode (pcc = 00h) note 2 9.5 19 ma f x = 8 mhz, crystal/ceramic oscillation operating mode (pcc = 00h) note 3 15 28.5 i dd3 rc oscillation operating mode (f xt = 40 khz) 180 560 a i dd4 rc oscillation halt mode (f xt = 40 khz) 60 180 i dd5 cl1 = v dd stop mode 130 422 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 (4) pd780814(a1), pd780816(a1) (t a = -40c to +110c, v dd = 4.0 to 5.5 v) mask rom version these specifications are only target values and may not be satisfied by mass-produced products. remark: the characteristics of the dual-function pins ar e the same as those of the port pins unless otherwise specified. parameter symbol conditions min. typ. max. unit high-level input voltage v ih1 p00 - p03, p10 - p17, p20 - p27, p40 - p47, p50 - p57, p60 - p67, p70, p71, crxd, ani0 - ani11 0.7 v dd v dd v v ih2 reset 0.8 v dd v dd v ih4 x1, x2, cl1 v dd - 0.5 v dd low-level input voltage v il1 p00 - p03, p10 - p17, p20 - p27, p40 - p47, p50 - p57, p60 - p67, p70, p71, crxd, ani0 - ani11 0 0.3 v dd v il2 reset 0 0.2 v dd v il4 x1, x2, cl1 0 0.4 high-level output voltage v oh1 p00 - p03, p10 - p17, p20 - p27, p40 - p47, p50 - p57, p60 - p67, p70, p71, ctxd v dd = 4.0 - 5.5 v i oh = -1 ma v dd - 1.0 v dd low-level output voltage v ol1 p00 - p03, p10 - p17, p20 - p27, p40 - p47, p50 - p57, p60 - p67, p70, p71, ctxd v dd = 4.0 - 5.5 v i ol = 1.6 ma 00.4 high-level input leakage current i lih1 p00 - p03, p10 - p17, p20 - p27, p40 - p47, p50 - p57, p60 - p67, p70, p71, reset , crxd, ani0 - ani11 v in = v dd 010 a i lih2 x1, x2, cl1, cl2 0 20 low-level input leakage current i lil1 p00 - p03, p10 - p17, p20 - p27, p40 - p47, p50 - p57, p60 - p67, p70, p71, reset , crxd, ani0 - ani11 v in = 0 v 0-10 ii lil2 x1, x2, cl1, cl2 0 -20 high-level output leakage current i loh v out = v dd 010 low-level output leakage current i lol v out = 0 v 0-10 software pull-up resistor r2 v in = 0 v 4.5 v d v dd d 5.5 v 10 30 100 k : 423 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 (5) pd780814(a1), pd780816(a1) (t a = -40c to +110c, v dd = 4.0 to 5.5 v) these specifications are only target values and may not be satisfied by mass-produced products. notes: 1. current through v dd0 , v dd1 respectively through v ss0 , v ss1 . excluded is the current through the inside pull-up resistors, through av dd /av ref , the port current. 2. cpu is operable. the other peripherals like: can controller, timer 0, timer 2, serial interfaces, a/d converter etc. are stopped. 3. cpu and all peripherals (except for the a/d converter) are in operating mode and pcl out- put is f x . remarks: 1. f x : main system clock oscillation frequency. 2. f xt : subsystem clock oscillation frequency. 3. the typical values are with respect to t a = 25c. parameter symbol test conditions min. typ. max. unit power supply current note 1 i dd1 f x = 8 mhz, crystal/ceramic oscillation operating mode (pcc = 00h) note 2 5.5 12 ma f x = 8 mhz, crystal/ceramic oscillation operating mode (pcc = 00h) note 3 9.5 20 i dd3 rc oscillation operating mode (f xt = 40 khz) 150 1560 a i dd4 rc oscillation halt mode (f xt = 40 khz) 60 1180 i dd5 cl1 = v dd stop mode 1 1000 424 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 (6) pd780814(a2), pd780816(a2) (t a = -40c to +125c, v dd = 4.0 to 5.5 v) mask rom version remark: the characteristics of the dual-function pins ar e the same as those of the port pins unless otherwise specified. parameter symbol conditions min. typ. max. unit high-level input voltage v ih1 p00 - p03, p10 - p17, p20 - p27, p40 - p47, p50 - p57, p60 - p67, p70, p71, crxd, ani0 - ani11 0.7 v dd v dd v v ih2 reset 0.8 v dd v dd v ih4 x1, x2, cl1 v dd - 0.5 v dd low-level input voltage v il1 p00 - p03, p10 - p17, p20 - p27, p40 - p47, p50 - p57, p60 - p67, p70, p71, crxd, ani0 - ani11 0 0.3 v dd v il2 reset 0 0.2 v dd v il4 x1, x2, cl1 0 0.4 high-level output voltage v oh1 p00 - p03, p10 - p17, p20 - p27, p40 - p47, p50 - p57, p60 - p67, p70, p71, ctxd v dd = 4.0 - 5.5 v i oh = -1 ma v dd - 1.0 v dd low-level output voltage v ol1 p00 - p03, p10 - p17, p20 - p27, p40 - p47, p50 - p57, p60 - p67, p70, p71, ctxd v dd = 4.0 - 5.5 v i ol = 1.6 ma 00.4 high-level input leakage current i lih1 p00 - p03, p10 - p17, p20 - p27, p40 - p47, p50 - p57, p60 - p67, p70, p71, reset , crxd, ani0 - ani11 v in = v dd 010 a i lih2 x1, x2, cl1, cl2 0 20 low-level input leakage current i lil1 p00 - p03, p10 - p17, p20 - p27, p40 - p47, p50 - p57, p60 - p67, p70, p71, reset , crxd, ani0 - ani11 v in = 0 v 0-10 ii lil2 x1, x2, cl1, cl2 0 -20 high-level output leakage current i loh v out = v dd 010 low-level output leakage current i lol v out = 0 v 0-10 software pull-up resistor r2 v in = 0 v 4.5 v d v dd d 5.5 v 10 30 100 k : 425 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 (7) pd780814(a2), pd780816(a2) (t a = -40c to +125c, v dd = 4.0 to 5.5 v) notes: 1. current through v dd0 , v dd1 respectively through v ss0 , v ss1 . excluded is the current through the inside pull-up resistors, through av dd /av ref , the port current. 2. cpu is operable. the other peripherals like: can controller, timer 0, timer 2, serial interfaces, a/d converter etc. are stopped. 3. cpu and all peripherals (except for the a/d converter) are in operating mode and pcl out- put is f x . remarks: 1. f x : main system clock oscillation frequency. 2. f xt : subsystem clock oscillation frequency. 3. the typical values are with respect to t a = 25c. parameter symbol test conditions min. typ. max. unit power supply current note 1 i dd1 f x = 8 mhz, crystal/ceramic oscillation operating mode (pcc = 00h) note 2 5.5 12 ma f x = 8 mhz, crystal/ceramic oscillation operating mode (pcc = 00h) note 3 9.5 20 i dd3 rc oscillation operating mode (f xt = 40 khz) 150 1560 a i dd4 rc oscillation halt mode (f xt = 40 khz) 60 1180 i dd5 cl1 = v dd stop mode 1 1000 426 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 24.6 ac characteristics 24.6.1 basic operation (1) pd780814(a), pd780816(a), pd78f0818(a) (t a = -40c to +85c, v dd = 4.0 to 5.5 v) notes: 1. the cycle time equals to the minimum instruction execution time. for example: 1 nop instruction corresponds to 2 cpu clock cycles (f cpu ) selected by the processor clock control register (pcc). 2. f smp2 (sampling clock) = f x /8, f x /16, f x /32, f x /64 3. f smp0 (sampling clock) = f x /2, f x /16, f x /128. selection of f smp0 = f x /2, f x /16, f x /128 is possible using bits 0 and 1 (prm00, prm01) of prescaler mode register prm0. however, if the ti00 valid edge is selected as the count clock, the value becomes f smp0 = f x /2. parameter symbol test conditions min. typ. max. unit cycle time note 1 t cy 4.0 v d v dd d 5.5 v 0.25 125 s ti50, ti51 input frequency f ti5 04mhz ti50, ti51 input high/low level width t tih5 t til5 100 ns ti20, ti21, ti22 input high/low level width t tih2 t til2 3/f smp2 note 2 s ti00, ti01 input high/low level width t caph t capl 3/f smp0 note 3 interrupt input high/low level width t inth t intl intp0 - intp3, p40 - p47 1 reset low level width t rsl 10 427 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 t cy vs. v dd 60 cycle time t cy [ s] 10 2.0 1.0 0.5 0.4 0 1234 56 supply voltage v dd [v] operation guaranteed range 428 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 (2) pd780814(a1), pd780816(a1) (t a = -40c to +110c, v dd = 4.0 to 5.5 v) these specifications are only target values and may not be satisfied by mass-produced products. notes: 1. the cycle time equals to the minimum instruction execution time. for example: 1 nop instruction corresponds to 2 cpu clock cycles (f cpu ) selected by the processor clock control register (pcc). 2. f smp2 (sampling clock) = f x /8, f x /16, f x /32, f x /64 3. f smp0 (sampling clock) = f x /2, f x /16, f x /128. selection of f smp0 = f x /2, f x /16, f x /128 is possible using bits 0 and 1 (prm00, prm01) of prescaler mode register prm0. however, if the ti00 valid edge is selected as the count clock, the value becomes f smp0 = f x /2. parameter symbol test conditions min. typ. max. unit cycle time note 1 t cy 4.5 v d v dd d 5.5 v 0.25 125 s 4.0 v d v dd d 5.5 v 0.5 125 ti50, ti51 input frequency f ti5 04mhz ti50, ti51 input high/low level width t tih5 t til5 100 ns ti20, ti21, ti22 input high/low level width t tih2 t til2 3/f smp2 note 2 s ti00, ti01 input high/low level width t caph t capl 3/f smp0 note 3 interrupt input high/low level width t inth t intl intp0 - intp3, p40 - p47 1 reset low level width t rsl 10 429 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 t cy vs. v dd 60 cycle time t cy [ s] 10 2.0 1.0 0.5 0.4 0 1234 56 supply voltage v dd [v] operation guaranteed range 430 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 (3) pd780814(a2), pd780816(a2) (t a = -40c to +125c, v dd = 4.0 to 5.5 v) notes: 1. the cycle time equals to the minimum instruction execution time. for example: 1 nop instruction corresponds to 2 cpu clock cycles (f cpu ) selected by the processor clock control register (pcc). 2. f smp2 (sampling clock) = f x /8, f x /16, f x /32, f x /64 3. f smp0 (sampling clock) = f x /2, f x /16, f x /128. selection of f smp0 = f x /2, f x /16, f x /128 is possible using bits 0 and 1 (prm00, prm01) of prescaler mode register prm0. however, if the ti00 valid edge is selected as the count clock, the value becomes f smp0 = f x /2. parameter symbol test conditions min. typ. max. unit cycle time note 1 t cy 4.5 v d v dd d 5.5 v 0.25 125 s 4.0 v d v dd d 5.5 v 0.5 125 ti50, ti51 input frequency f ti5 04mhz ti50, ti51 input high/low level width t tih5 t til5 100 ns ti20, ti21, ti22 input high/low level width t tih2 t til2 3/f smp2 note 2 s ti00, ti01 input high/low level width t caph t capl 3/f smp0 note 3 interrupt input high/low level width t inth t intl intp0 - intp3, p40 - p47 1 reset low level width t rsl 10 431 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 t cy vs. v dd 60 cycle time t cy [ s] 10 2.0 1.0 0.5 0.4 0 1234 56 supply voltage v dd [v] operation guaranteed range 432 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 24.6.2 serial interface (1) pd780814(a), pd780816(a), pd78f0818(a) (t a = -40c to +85c, v dd = 4.0 to 5.5 v) (a) serial interface channel csi (sio2) 3-wire serial i/o mode (sck2 internal clock output) note: c is the load capacitance of so2, sck2 output line 3-wire serial i/o mode (sck2 external clock output) note: c is the load capacitance of so2, sck2 output line parameter symbol conditions min. max. unit sck2 cycle time t kcy1 1000 ns sck2 high/low-level width t kh1 , t kl1 t kcy1 /2 - 50 si2 setup time (to sck2 ) n t sik1 100 si2 hold time (from sck2 ) n t ksi1 400 so2 output delay time (from sck2 ) p t kso1 c = 100 pf note 300 parameter symbol conditions min. max. unit sck2 cycle time t kcy1 800 ns sck2 high/low-level width t kh1 , t kl1 400 si2 setup time (to sck2 ) n t sik1 100 si2 hold time (from sck2 ) n t ksi1 400 so2 output delay time (from sck2 ) p t kso1 c = 100 pf note 300 433 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 (b) serial interface channel csi (sio3) 3-wire serial i/o mode (sck3 internal clock output) note: c is the load capacitance of so3, sck3 output line 3-wire serial i/o mode (sck3 external clock output) note: c is the load capacitance of so3, sck3 output line (c) serial interface channel uart uart mode (dedicated baud rate generator output) parameter symbol conditions min. max. unit sck3 cycle time t kcy1 1000 ns sck3 high/low-level width t kh1 , t kl1 t kcy1 /2 - 50 si3 setup time (to sck3 ) n t sik1 100 si3 hold time (from sck3 ) n t ksi1 400 so3 output delay time (from sck3 ) p t kso1 c = 100 pf note 300 parameter symbol conditions min. max. unit sck3 cycle time t kcy1 800 ns sck3 high/low-level width t kh1 , t kl1 400 si3 setup time (to sck3 ) n t sik1 100 si3 hold time (from sck3 ) n t ksi1 400 so3 output delay time (from sck3 ) p t kso1 c = 100 pf note 300 parameter symbol conditions min. typ. max. unit transfer rate 125 kbps 434 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 (2) pd780814(a1), pd780816(a1) (t a = -40c to +110c, v dd = 4.0 to 5.5 v) mask version (a) serial interface channel csi (sio2) these specifications are only target values and may not be satisfied by mass-produced products. 3-wire serial i/o mode (sck2 internal clock output) note: c is the load capacitance of so2, sck2 output line these specifications are only target values and may not be satisfied by mass-produced products. 3-wire serial i/o mode (sck2 external clock output) note: c is the load capacitance of so2, sck2 output line parameter symbol conditions min. max. unit sck2 cycle time t kcy1 1000 ns sck2 high/low-level width t kh1 , t kl1 t kcy1 /2 - 50 si2 setup time (to sck2 ) n t sik1 100 si2 hold time (from sck2 ) n t ksi1 400 so2 output delay time (from sck2 ) p t kso1 c = 100 pf note 300 parameter symbol conditions min. max. unit sck2 cycle time t kcy1 800 ns sck2 high/low-level width t kh1 , t kl1 400 si2 setup time (to sck2 ) n t sik1 100 si2 hold time (from sck2 ) n t ksi1 400 so2 output delay time (from sck2 ) p t kso1 c = 100 pf note 300 435 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 (b) serial interface channel csi (sio3) these specifications are only target values and may not be satisfied by mass-produced products. 3-wire serial i/o mode (sck3 internal clock output) note: c is the load capacitance of so3, sck3 output line these specifications are only target values and may not be satisfied by mass-produced products. 3-wire serial i/o mode (sck3 external clock output) note: c is the load capacitance of so3, sck3 output line (c) serial interface channel uart these specifications are only target values and may not be satisfied by mass-produced products. uart mode (dedicated baud rate generator output) parameter symbol conditions min. max. unit sck3 cycle time t kcy1 1000 ns sck3 high/low-level width t kh1 , t kl1 t kcy1 /2 - 50 si3 setup time (to sck3 ) n t sik1 100 si3 hold time (from sck3 ) n t ksi1 400 so3 output delay time (from sck3 ) p t kso1 c = 100 pf note 300 parameter symbol conditions min. max. unit sck3 cycle time t kcy1 800 ns sck3 high/low-level width t kh1 , t kl1 400 si3 setup time (to sck3 ) n t sik1 100 si3 hold time (from sck3 ) n t ksi1 400 so3 output delay time (from sck3 ) p t kso1 c = 100 pf note 300 parameter symbol conditions min. typ. max. unit transfer rate 125 kbps 436 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 (3) pd780814(a2), pd780816(a2) (t a = -40c to +125c, v dd = 4.0 to 5.5 v) (a) serial interface channel csi (sio2) 3-wire serial i/o mode (sck2 internal clock output) note: c is the load capacitance of so2, sck2 output line 3-wire serial i/o mode (sck2 external clock output) note: c is the load capacitance of so2, sck2 output line parameter symbol conditions min. max. unit sck2 cycle time t kcy1 1000 ns sck2 high/low-level width t kh1 , t kl1 t kcy1 /2 - 50 si2 setup time (to sck2 ) n t sik1 100 si2 hold time (from sck2 ) n t ksi1 400 so2 output delay time (from sck2 ) p t kso1 c = 100 pf note 300 parameter symbol conditions min. max. unit sck2 cycle time t kcy1 800 ns sck2 high/low-level width t kh1 , t kl1 400 si2 setup time (to sck2 ) n t sik1 100 si2 hold time (from sck2 ) n t ksi1 400 so2 output delay time (from sck2 ) p t kso1 c = 100 pf note 300 437 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 (b) serial interface channel csi (sio3) 3-wire serial i/o mode (sck3 internal clock output) note: c is the load capacitance of so3, sck3 output line 3-wire serial i/o mode (sck3 external clock output) note: c is the load capacitance of so3, sck3 output line (c) serial interface channel uart uart mode (dedicated baud rate generator output) parameter symbol conditions min. max. unit sck3 cycle time t kcy1 1000 ns sck3 high/low-level width t kh1 , t kl1 t kcy1 /2 - 50 si3 setup time (to sck3 ) n t sik1 100 si3 hold time (from sck3 ) n t ksi1 400 so3 output delay time (from sck3 ) p t kso1 c = 100 pf note 300 parameter symbol conditions min. max. unit sck31 cycle time t kcy1 800 ns sck31 high/low-level width t kh1 , t kl1 400 si31 setup time (to sck31 ) n t sik1 100 si31 hold time (from sck31 ) n t ksi1 400 so31 output delay time (from sck31 ) p t kso1 c = 100 pf note 300 parameter symbol conditions min. typ. max. unit transfer rate 125 kbps 438 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 ac timing test points (excluding x1, cl1 input) clock timing ti timing 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points t xl t xh 1/f x v dd ? 0.5 v 0.4 v t xtl t xth 1/f xt v dd ? 0.5 v 0.4 v x1 input cl1 input t capl t caph ti00, ti01 ti20, ti21, ti22 t tih2 t til2 439 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 3-wire serial i/o mode / 2-wire serial i/o mode remark: n = 2, 3 t kcy1 t kl1 t kh1 sckn sin son t sik1 t ksi1 t kso1 input data output data 440 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 24.6.3 a/d converter characteristics (1) pd780814(a), pd780816(a), pd78f0818(a) (t a = -40c to +85c, v dd = 4.0 to 5.5 v, av ss = v ss = 0 v, f x = 8 mhz) note: overall error excluding quantization ( 1/2 lsb). it is indicated as a ratio to the full-scale value. remark: f x : main system clock oscillation frequency. (2) pd780814(a1), pd780816(a1) (t a = -40c to +110c, v dd = 4.0 to 5.5 v, av ss = v ss = 0 v, f x = 8 mhz) these specifications are only target values and may not be satisfied by mass-produced products. remark: f x : main system clock oscillation frequency. parameter symbol test conditions min. typ. max. unit resolution 8 8 8 bit overall error note 0.6 % conversion time t conv 14 s analog input voltage v ian av ss av dd v reference voltage av dd / av ref v dd v dd v dd av dd /av ref current i ref adcs-bit = 1 750 1500 a adcs-bit = 0 0 3 parameter symbol test conditions min. typ. max. unit resolution 8 8 8 bit overall error 1.3 % conversion time t conv 14 s analog input voltage v ian av ss av dd v reference voltage av dd / av ref v dd v dd v dd av dd /av ref current i ref adcs-bit = 1 750 1500 a adcs-bit = 0 0 3 441 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 (3) pd780814(a2), pd780816(a2) (t a = -40c to +125c, v dd = 4.0 to 5.5 v, av ss = v ss = 0 v, f x = 8 mhz) remark: f x : main system clock oscillation frequency. parameter symbol test conditions min. typ. max. unit resolution 8 8 8 bit overall error 1.3 % conversion time t conv 14 s analog input voltage v ian av ss av dd v reference voltage av dd / av ref v dd v dd v dd av dd /av ref current i ref adcs-bit = 1 750 1500 a adcs-bit = 0 0 3 442 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 24.6.4 data memory stop mode low supply voltage data retention characteristics (1) pd780814(a), pd780816(a), pd78f0818(a) (t a = -40c to +85c) note: in combination with bits 0 to 2 (osts0 to osts2) of oscillation stabilization time select register, selection of 2 12 /f x and 2 14 /f x to 2 17 /f x is possible. remark: f x : main system clock oscillation frequency. (2) pd780814(a1), pd780816(a1) (t a = -40c to +110c) these specifications are only target values and may not be satisfied by mass-produced products. note: in combination with bits 0 to 2 (osts0 to osts2) of oscillation stabilization time select register, selection of 2 12 /f x and 2 14 /f x to 2 17 /f x is possible. remark: f x : main system clock oscillation frequency. parameter symbol test conditions min. typ. max. unit data retention power supply voltage v dddr 2.0 5.5 v data retention power supply current i dddr v dddr = 2.0 v 130a release signal set time t srel 0s oscillation stabilization wait time t wait release by reset 2 17 /f x ms release by interrupt note parameter symbol test conditions min. typ. max. unit data retention power supply voltage v dddr 2.5 5.5 v data retention power supply current i dddr v dddr = 2.0 v 11000a release signal set time t srel 0s oscillation stabilization wait time t wait release by reset 2 17 /f x ms release by interrupt note 443 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 (3) pd780814(a2), pd780816(a2) (t a = -40c to +125c) note: in combination with bits 0 to 2 (o sts0 to osts2) of oscillation st abilization time select register, selection of 2 12 /f x and 2 14 /f x to 2 17 /f x is possible. remark: f x : main system clock oscillation frequency. parameter symbol test conditions min. typ. max. unit data retention power supply voltage v dddr 2.5 5.5 v data retention power supply current i dddr v dddr = 2.0 v 1 1000 a release signal set time t srel 0s oscillation stabilization wait time t wait release by reset 2 17 /f x ms release by interrupt note 444 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 data retention timing (sto p mode release by reset) data retention timing (standby release signal: stop mode release by interrupt signal) interrupt input timing reset input timing t srel t wait v dd reset stop instruction execution stop mode data retension mode internal reset operation halt mode operating mode v dddr t srel t wait v dd stop instruction execution stop mode data retension mode halt mode operating mode standby release signal (interrupt request) v dddr t intl t inth intp0 - intp3 t rsl reset 445 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 24.6.5 flash memory programming characteristics: pd78f0818(a) (t a = 10c to 40c, v dd = av dd = 4.5 to 5.5 v, v ss = av ss = 0 v, v pp = 9.7 to 10.3 v) (1) basic characteristics note: operation is not guaranteed for over 20 rewrites. remark: after execution of the program command, execute the verify command and check that the writing has been completed normally. (2) serial write operation characteristics note: for maximum t ch / t cl , please make sure to finish the pulses within the time t count . parameter symbol conditions min. typ. max. unit operating frequency f x 4.0 8.38 mhz supply voltage v dd 4.0 5.5 v v ppl when v pp low-level is detected 0 0.2 v dd v v pp when v pp high-level is detected 0.8 v dd v dd 1.2 v dd v v pph when v pp high-voltage is detected and for programming 9.7 10.0 10.3 v number of rewrites c wrt 20 note times programming temperature t prg 10 +40 q c parameter symbol conditions min. typ. max. unit set time from v dd n to v pp n t drpsr v pp high voltage 10 s set time from v pp n to reset n t psrrf v pp high voltage 1.0 v pp n count start time from reset n t rfcf v pp high voltage 1.0 count execution time t count 2.0 ms v pp counter high-level width t ch 8.0 note s v pp counter low-level width t cl 8.0 note v pp counter rise/fall time t r , t f 1.0 446 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 flash write mode setting timing reset (input) 0 v drpsr t psrrf t rfcf t cl t r t f t ch t count t dd v dd v dd v dd v ppl v pph v 0 v pp v 447 chapter 24 electrical specifications user?s manual u15251ee4v0ud00 (3) write erase characteristics notes: 1. the recommended setting value for the step erase time is 0.2 s. 2. the prewrite time before erasure and the erase verify time (write-back time) is not included. 3. the recommended setting value for the write-back time is 50 ms. 4. write-back is executed once by the issuance of the write-back command. therefore, the number of retries must be the maximum value minus the number of commands issued. 5. recommended step write setting value is 50 s. 6. the actual write time per word is 100 s longer. the internal verify time during or after a write is not included. 7. when a product is first written after shipment, "erase o write" and "write only" are both taken as one rewrite. example: p: write, e: erase shipped product o p o e o p o e o p : 3 rewrites shipped product o e o p o e o p o e o p : 3 rewrites remarks: 1. the range of the operating clock during flash memory programming is the same as the range during normal operation. 2. when using the flash master, the time parameters that need to be downloaded from the parameter files for write/erase are automatically set. unless otherwise directed, do not change the set values. parameter symbol conditions min. typ. max. unit v pp supply voltage v pp2 during flash memory programming 9.7 10.0 10.3 v v dd supply current i dd when v pp = 10 v, f x = 8.38 mhz 50 ma v pp supply current i pp when v pp = 10 v 100 ma step erase time t er note 1 0.2 s overall erase time per area t era when step erase time = 0.2 s note 2 20 s/area write-back time t wb note 3 49.4 50 50.6 ms number of write-backs per write-back command c wb when write-back time = 50 ms note 4 60 times/ write-back command number of erase/ write-backs c erwb 16 times step write time t wr note 5 48 50 52 s overall write time per word t wrw when step write time = 50 s (1 word = 1 byte) note 6 48 520 s/ word number of rewrites per area c erwr 1 erase + 1 write after erase = = 1 rewrite note 7 20 times/ area 448 user?s manual u15251ee4v0ud00 [memo] 449 user?s manual u15251ee4v0ud00 chapter 25 package drawing remark: the shape and material of the es product is the same as the mass produced product. 48 32 33 64 1 17 16 49 s s 64-pin plastic tqfp (12x12) item millimeters g 1.125 a 14.00.2 c 12.00.2 d f 1.125 14.00.2 b 12.00.2 n 0.10 p q 0.10.05 1.0 s r 3 +4 -3 r h k j q g i s p detail of lead end note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. m h 0.32 +0.06 -0.10 i 0.13 j k 1.00.2 0.65 (t.p.) l 0.5 m 0.17 +0.03 -0.07 p64gk-65-9et-2 t u 0.60.15 0.25 f m a b cd n t l u 1.10.1 450 user?s manual u15251ee4v0ud00 [memo] 451 user?s manual u15251ee4v0ud00 chapter 26 recommended soldering conditions the pd780816 subseries should be soldered and mounted under the conditions in the table below. for detail of recommended soldering conditions, refer to the information document semiconductor device mounting technology manual (iei-1207) . for soldering methods and conditions other than those recommended below, consult our sales personnel. pd780814gk(a)-xxx-9et : 64-pin plastic qfp (12 u 12 mm) pd780814gk(a1)-xxx-9et : 64-pin plastic qfp (12 u 12 mm) pd780814gk(a2)-xxx-9et : 64-pin plastic qfp (12 u 12 mm) pd780816gk(a)-xxx-9et : 64-pin plastic qfp (12 u 12 mm) pd780816gk(a1)-xxx-9et : 64-pin plastic qfp (12 u 12 mm) pd780816gk(a2)-xxx-9et : 64-pin plastic qfp (12 u 12 mm) pd78f0818gk(a)-xxx-9et : 64-pin plastic qfp (12 u 12 mm) surface mounting type soldering conditions caution: use of more than one soldering method should be avoided (except in the case of pin part heating). soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 q c. duration: 30 sec max. (at 210 q c or above). number of times: twice max. 452 user?s manual u15251ee4v0ud00 [memo] 453 user?s manual u15251ee4v0ud00 appendix a development tools the following development tools are available for the development of systems that employ the pd780816 subseries. figure a-1 shows the development tool configuration. support for pc98-nx series unless otherwise specified, products compatible with ibm pc/attm computers are compatible with pc98-nx series computers. when using pc98-nx series computers, refer to the explanation for ibm pc/at computers. windows (unless otherwise specified, ?windows? means the following os). windows 95/98 windows nt version 4.0 windows 2000 454 appendix a development tools user?s manual u15251ee4v0ud00 figure a-1: development tool configuration (a) when using the in-circuit emulator ie-78k0-ns-a remark: items in broken line boxes differ according to the development environment. see a.3.1 hardware. system simulator integrated debugger device file embedded software real-time os os debugging tool assembler package c compiler package c library source file device file language processing software flash memory write adapter in-circuit emulator power supply unit emulation probe conversion socket or conversion adapter target system host machine (pc) interface adapter, pc card interface, etc. emulation board on-chip flash memory version flash memory write environment flash programmer i/o board performance board 455 appendix a development tools user?s manual u15251ee4v0ud00 a.1 language processing software nec software iar software a.2 flash memory writing tools ra78k/0 assembler package this assembler converts programs written in mnemonics into an object codes executa- ble with a microcontroller. further, this assembler is provided with f unctions capable of automatically creating symbol tables and branch instruction optimization. this assembler should be used in combination with an optional device file. 456 appendix a development tools user?s manual u15251ee4v0ud00 a.3 debugging tools a.3.1 hardware (1) when using the in-circuit emulator ie-78k0-ns-a (2) socket details ie-78k0-ns-a in-circuit emulator the in-circuit emulator serves to debug hardware and software when developing application systems using a 78k/0 series product. it corres ponds to integrated debugger (id78k0-ns). this emulator s hould be used in combination with power supply unit, emulation probe, and interface ada pter which is required to connect this emulator to the host machine. ie-70000-mc-ps-b power supply unit this adapter is used for supplying power from a receptacle of 100-v to 240-v ac. eb-power fw 7301/05 power supply unit this adapter is used for supplying power from a receptable of 100 v to 240 v ac ie-70000-98-if-c interface adapter this adapter is required when using the pc-9800 series computer (except note- book type) as the ie-78k0-ns-a host machine (c bus compatible). ie-70000-cd-if-a pc card interface this is pc card and interface cable required when using notebook-type computer as the ie-78k0-ns-a host machine (pcmcia socket compatible). ie-70000-pc-if-c interface adapter this adapter is required when using the ibm pc compatible computers as the ie- 78k0-ns-a host machi ne (isa bus compatible). ie-70000-pci-if-a interface adapter this adapter is required when using a co mputer with pci bus as the ie-78k0-ns host machine. ie-78k0-ns-p04 emulation board this board emulates the operations of the peripheral hardware peculiar to a device. it should be used in combination with an in-circuit emulator. ie-780818-ns-em4 probe board this board provides the connection and buffers between the emulation board and the connector of the emulation probe. np-64gk emulation probe this probe is used to connect the in-cir cuit emulator to a target system and is designed for use with 64-pin plastic qfp. nqpack064sb yqpack064sb yqsocket064sbf hqpack064sb1410 conversion adapter this conversion adapter co nnects the np-64gk to a ta rget system board designed for a 64-pin plastic qfp. nqpack064sb socket for soldering on the target. yqpack064sb adapter socket for connec ting the probe to the nqpack064sb hqpack064sb140 lid socket for connecting the device to the nqpack064sb yqsocket064sbf high adapter between the device to the yqpack064sb and the probe 457 appendix a development tools user?s manual u15251ee4v0ud00 a.3.2 software sm78k0 system simulator this system simulator is used to perform debugging at c source level or assem- bler level while simulating the operation of the target system on a host machine. this simulator runs on windows. use of the sm78k0 allows the executi on of application logical testing and per- formance testing on an independent basis from hardware development without having to use an in-circuit emulator, thereby providing higher development effi- ciency and software quality. the sm78k0 should be used in combination with the optional device file. id78k0-ns integrated debugger (supporting in-circuit emulator ie-78k0-ns-a) this debugger is a control program to debug 78k/0 series microcontrollers. it adopts a graphical user interface, which is equivalent visually and operationally to windows or osf/motif?. it also has an enhanced debugging function for c language programs, and thus trace results can be displayed on screen in c-lan- guage level by using the windows integration function which links a trace result with its source program, disassembled display, and memory display. in addition, by incorporating function modules such as task debugger and system perform- ance analyzer, the efficiency of debugging programs, which run on real-time oss can be improved. it should be used in combination with the optional device file. 458 user?s manual u15251ee4v0ud00 [memo] 459 user?s manual u15251ee4v0ud00 appendix b embedded software for efficient development and maintenance of the pd780816 subseries, the following embedded soft- ware products are available. b.1 real-time os caution: when purchasing the rx78k/0, fill in the purchase application form in advance and sign the user agreement. b.2 fuzzy inference development support system rx78k/0 real-time os rx78k/0 is a real-time os conforming with the itron specifications. tool (configura- tor) for generating nucleus of rx78k/0 and plural information tables is supplied. used in combination with an optional assembler package (ra78k/0) and device file mx78k0 os tron specification subset os. nucleus of mx78k0 is supplied. this os performs task management, event management, and time management. it controls the task exe- cution sequence for task management and selects the task to be executed next. fe9000/fe9200 fuzzy knowledge data creation tool program that supports input, edit, and evaluation (simulation) of fuzzy knowledge data (fuzzy rule and membership function). fe9200 works on windows. part number: sxxxxfe9000 (pc-9800 series) sxxxxfe9200 (ibm pc/at a nd compatible machines) ft9080/ft9085 program that translates fuzzy knowledge data obtained by using fuzzy knowledge. translator data creation tool into assembler source program for ra78k0. part number: sxxxxft9080 (pc-9800 series) sxxxxft9085 (ibm pc/at an d compatible machines) fi78k0 program that executes fuzzy inference. executes fuzzy inference when linked with fuzzy inference module, fuzzy knowled ge data translated by translator. part number: sxxxxfi78k0 (pc-9800 series, ibm pc/at and compatible machines) fd78k0 fuzzy inference debugger support software for evaluation and adjustment of fuzzy knowledge data by using in- circuit emulator and at hardware level. part number: sxxxxfd78k0 (pc-9800 seri es, pc/at and compatible machines) 460 user?s manual u15251ee4v0ud00 [memo] 461 user?s manual u15251ee4v0ud00 appendix c register index numerics 8-bit timer mode control register 50 (tmc50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 8-bit timer mode control register 51 (tmc51) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 8-bit timer registers 50 and 51 (tm50, tm51) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 16-bit timer mode control register (tmc0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 16-bit timer mode control register (tmc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 16-bit timer output control register (toc0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 16-bit timer register (tm0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 16-bit timer register (tm2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 a a/d conversion result register (adcr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 a/d converter mode register (adm1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 analog input channel specification register (ads1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 05 asynchronous serial interface mode register (asim0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250, 256 asynchronous serial interface status register (asis0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252, 258 b baud rate generator control register (brgc0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253, 259 bit rate prescaler register (brprs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 c can control register (canc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 can receive error counter (rec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 can transmit error counter (tec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 capture pulse control register (crc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 capture register 20 (cr20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 capture register 21 (cr21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 capture register 22 (cr22). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 capture/compare control register 0 (crc0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 capture/compare register 00 (cr00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 capture/compare register 01 (cr01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 clock monitor mode register (clm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 clock output selection register (cks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 compare register 50 and 51 (cr50, cr51) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 57 d d/a converter mode register (dam0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 dcan error status register (canes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 e external interrupt falling edge enab le register (egn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 55 external interrupt rising edge enable register (egp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 55 f flash self-programming mode control register (flpmc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 g general registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 462 appendix c register index user?s manual u15251ee4v0ud00 i internal expansion ram size switching register (ixs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 interrupt mask flag registers (mk0l, mk0h, mk1l, mk1h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 interrupt request flag registers (if0l, if0h, if1l, if1h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 52 k key return mode register (krm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91, 370 m mask control register (maskc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 mask identifier control register (mcon) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 memory size switching register (ims) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 message count register (mcnt). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 o oscillation control register ( spoc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 oscillation stabilization ti me select register (osts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 p port function register (pf2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 port mode register 2 (pm2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162, 200 port mode register 4 (pm4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 port mode register 7 (pm7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 port mode registers (pm0, pm2, pm4 to pm7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 power-fail compare mode register (pfm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 power-fail compare threshold value register (pft) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 prescaler mode register (prm2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 prescaler mode register 0 (prm0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 priority specify flag registers (pr0l, pr0h, pr1l, pr1h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 processor clock control register (pcc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 program counter (pc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 program status word (psw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57, 356 pull-up resistor option register (pu0, pu2, pu4 to pu7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 r receive buffer register (rxb0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 receive data buffer status register (srbs20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220, 224, 228 receive message register (rmes). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 receive shift register 1 (rxs0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 redefinition control register (redef). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 s serial i/f data buffer register (sirb20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224, 228 serial i/f operation mode register (csim20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 serial i/f operation mode register 20 (csim20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 serial i/f receive data buffer register (sirb20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 serial i/o shift register (sio20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 serial i/o shift register (sio30). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 serial mode switch register (sioswi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239, 242, 2 44 serial operation mode register (csim30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 special function register (sfr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61, 73 successive approximation register (sar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 synchronization control registers (sync0 and sync1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 463 appendix c register index user?s manual u15251ee4v0ud00 t timer clock select register 50 (tcl50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 timer clock select register 51 (tcl51) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 transmit control register (tcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 transmit shift register 1 (txs0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 w watch timer mode register (wtm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 watchdog timer clock select register (wdcs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 watchdog timer mode register (wdtm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 464 user?s manual u15251ee4v0ud00 465 user?s manual u15251ee4v0ud00 appendix d revision history the following shows the revision history up to present. application portions signifies the chapter of each edition. table 1-0: (1/2) edition no. major items revised revised sections ee4 revision of chapter 1 (page 29) 1.6 revision of figure 11-1 (page 191) 11.2 revision of figure 16-2 (page 251), caution added 16.4 revision of figure 16-4 (page 254), caution added 16.4 revision of caution in figure 16-5 (page 255) 16.5 revision of caution in figure 16-6 (page 257) 16.5 revision of caution in figure 16-8 (page 260) 16.5 revision of table 16-4 (page 262) 16.5 addition of caution in figure 16-9 (page 262) 16.5 revision of caution in figure 16-12 (page 266) 16.5 rxonly-mode deleted (pages 322, 325) 17 can controller precautions added (page 345) 17.19 revision of figure 22-3 (page 386) 22.3 revision of chapter 24.5 (pages 407, 408, 409, 421. 423) 24.5 revision of chapter 24.6.1 ( pages 424, 426, 428) 24.6.1 revision of chapter 26 (page 449) 26 466 appendix d revision history user?s manual u15251ee4v0ud00 table 1-0: (2/2) edition no. major items revised revised sections although nec has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. despite all the care and precautions we've taken, you may encounter problems in the documentation. please complete this form whenever you'd like to report errors or suggest improvements to us. hong kong, philippines, oceania nec electronics hong kong ltd. fax: +852-2886-9022/9044 korea nec electronics hong kong ltd. seoul branch fax: 02-528-4411 taiwan nec electronics taiwan ltd. fax: 02-2719-5951 address north america nec electronics america inc. corporate communications dept. fax: 1-800-729-9288 1-408-588-6130 europe nec electronics (europe) gmbh market communication dept. fax: +49(0)-211-6503-1344 asian nations except philippines nec electronics singapore pte. ltd. fax: +65-6250-3583 japan nec semiconductor technical hotline i would like to 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